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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
PM7384
FREEDMTM-84P672
FRAME ENGINE AND DATALINK MANAGER 84P672
DATA SHEET
PROPRIETARY AND CONFIDENTIAL ISSUE 5: AUGUST 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
REVISION HISTORY Issue No. Issue 1 Issue 2 Issue 3 Issue 4 Issue 5 Issue Date April 10, 1999 July 7, 1999 January, 2000 July, 2000 August, 2001 Details of Change Document created. Document reissue. Document reissue. Document reissue. Minor corrections and changes to some DC and AC timing parameters. Patent information added. Change bars reflect issue 4.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
CONTENTS 1 2 3 4 5 6 7 8 9 FEATURES...............................................................................................1 APPLICATIONS........................................................................................3 REFERENCES .........................................................................................4 APPLICATION EXAMPLES ......................................................................5 BLOCK DIAGRAM....................................................................................6 DESCRIPTION .........................................................................................7 PIN DIAGRAM ..........................................................................................9 PIN DESCRIPTION ................................................................................10 FUNCTIONAL DESCRIPTION ...............................................................33 9.1 9.2 9.3 9.4 SCALEABLE BANDWIDTH INTERCONNECT (SBI) INTERFACE .....................................................................................................33 HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL.........34 SBI EXTRACTER AND PISO.......................................................35 RECEIVE CHANNEL ASSIGNER ................................................35 9.4.1 9.4.2 9.4.3 9.4.4 9.5 LINE INTERFACE..........................................................37 PRIORITY ENCODER ...................................................38 CHANNEL ASSIGNER ..................................................38 LOOPBACK CONTROLLER .........................................38
RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER...38 9.5.1 9.5.2 HDLC PROCESSOR .....................................................39 PARTIAL PACKET BUFFER PROCESSOR ..................39
9.6
RECEIVE DMA CONTROLLER ...................................................41 9.6.1 DATA STRUCTURES ....................................................42
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
9.6.2 9.6.3 9.6.4 9.6.5 9.7
DMA TRANSACTION CONTROLLER...........................52 WRITE DATA PIPELINE/MUX .......................................52 DESCRIPTOR INFORMATION CACHE ........................52 FREE QUEUE CACHE ..................................................53
PCI CONTROLLER......................................................................53 9.7.1 9.7.2 9.7.3 9.7.4 9.7.5 MASTER MACHINE ......................................................54 MASTER LOCAL BUS INTERFACE..............................56 TARGET MACHINE .......................................................57 CBI BUS INTERFACE ...................................................59 ERROR / BUS CONTROL .............................................59
9.8
TRANSMIT DMA CONTROLLER.................................................59 9.8.1 9.8.2 9.8.3 9.8.4 9.8.5 9.8.6 DATA STRUCTURES ....................................................60 TASK PRIORITIES ........................................................72 DMA TRANSACTION CONTROLLER...........................72 READ DATA PIPELINE..................................................72 DESCRIPTOR INFORMATION CACHE ........................72 FREE QUEUE CACHE ..................................................73
9.9
TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER73 9.9.1 9.9.2 TRANSMIT HDLC PROCESSOR..................................73 TRANSMIT PARTIAL PACKET BUFFER PROCESSOR74
9.10
TRANSMIT CHANNEL ASSIGNER .............................................76 9.10.1 9.10.2 9.10.3 LINE INTERFACE..........................................................78 PRIORITY ENCODER ...................................................79 CHANNEL ASSIGNER ..................................................79
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
9.11 9.12 9.13 9.14 10
SBI INSERTER AND SIPO ..........................................................79 PERFORMANCE MONITOR .......................................................80 JTAG TEST ACCESS PORT INTERFACE...................................80 PCI HOST INTERFACE ...............................................................80
NORMAL MODE REGISTER DESCRIPTION ........................................87 10.1 PCI HOST ACCESSIBLE REGISTERS .......................................87
11
PCI CONFIGURATION REGISTER DESCRIPTION ............................284 11.1 PCI CONFIGURATION REGISTERS.........................................284
12
TEST FEATURES DESCRIPTION .......................................................295 12.1 12.2 TEST MODE REGISTERS ........................................................295 JTAG TEST PORT .....................................................................297 12.2.1 12.2.2 IDENTIFICATION REGISTER .....................................297 BOUNDARY SCAN REGISTER ..................................298
13
OPERATIONS ......................................................................................314 13.1 JTAG SUPPORT........................................................................314
14
FUNCTIONAL TIMING .........................................................................321 14.1 14.2 14.3 14.4 14.5 SBI DROP BUS INTERFACE TIMING .......................................321 SBI ADD BUS INTERFACE TIMING ..........................................322 RECEIVE LINK TIMING.............................................................322 TRANSMIT LINK TIMING ..........................................................323 PCI INTERFACE ........................................................................323
15 16 17
ABSOLUTE MAXIMUM RATINGS........................................................333 D.C. CHARACTERISTICS....................................................................334 FREEDM-84P672 TIMING CHARACTERISTICS.................................336
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
18 19
ORDERING AND THERMAL INFORMATION ......................................344 MECHANICAL INFORMATION.............................................................345
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
LIST OF FIGURES FIGURE 1 - HDLC FRAME...............................................................................34 FIGURE 2 - CRC GENERATOR.......................................................................35 FIGURE 3 - PARTIAL PACKET BUFFER STRUCTURE ..................................40 FIGURE 4 - RECEIVE PACKET DESCRIPTOR...............................................42 FIGURE 5 - RECEIVE PACKET DESCRIPTOR TABLE...................................45 FIGURE 6 - RPDRF AND RPDRR QUEUES ...................................................48 FIGURE 7 - RPDRR QUEUE OPERATION......................................................50 FIGURE 8 - RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.........51 FIGURE 9 - GPIC ADDRESS MAP ..................................................................58 FIGURE 10 - TRANSMIT DESCRIPTOR .........................................................60 FIGURE 11 - TRANSMIT DESCRIPTOR TABLE .............................................64 FIGURE 12 - TDRR AND TDRF QUEUES .......................................................66 FIGURE 13 - TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE ....68 FIGURE 14 - TD LINKING................................................................................71 FIGURE 15 - PARTIAL PACKET BUFFER STRUCTURE ................................75 FIGURE 16 - INPUT OBSERVATION CELL (IN_CELL) ................................. 311 FIGURE 17 - OUTPUT CELL (OUT_CELL) ...................................................312 FIGURE 18 - BI-DIRECTIONAL CELL (IO_CELL) .........................................312 FIGURE 19 - LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS ..............................................................................................................313 FIGURE 20 - BOUNDARY SCAN ARCHITECTURE ......................................315 FIGURE 21 - TAP CONTROLLER FINITE STATE MACHINE ........................317 FIGURE 22 - T1/E1 DROP BUS FUNCTIONAL TIMING................................321
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
FIGURE 23 - DS3 DROP BUS FUNCTIONAL TIMING ..................................321 FIGURE 24 - DS3 ADD BUS ADJUSTMENT REQUEST FUNCTIONAL TIMING ..............................................................................................................322 FIGURE 25 - RECEIVE LINK TIMING............................................................323 FIGURE 26 - TRANSMIT LINK TIMING .........................................................323 FIGURE 27 - PCI READ CYCLE ....................................................................325 FIGURE 28 - PCI WRITE CYCLE ..................................................................326 FIGURE 29 - PCI TARGET DISCONNECT ....................................................327 FIGURE 30 - PCI TARGET ABORT................................................................328 FIGURE 31 - PCI BUS REQUEST CYCLE ....................................................328 FIGURE 32 - PCI INITIATOR ABORT TERMINATION ...................................329 FIGURE 33 - PCI EXCLUSIVE LOCK CYCLE ...............................................330 FIGURE 34 - PCI FAST BACK TO BACK.......................................................332 FIGURE 35 - SBI FRAME PULSE TIMING ....................................................337 FIGURE 36 - SBI DROP BUS TIMING ...........................................................338 FIGURE 37 - SBI ADD BUS TIMING ..............................................................339 FIGURE 38 - SBI ADD BUS COLLISION AVOIDANCE TIMING ....................339 FIGURE 39 - RECEIVE DATA TIMING...........................................................340 FIGURE 40 - TRANSMIT DATA TIMING ........................................................340 FIGURE 41 - PCI INTERFACE TIMING .........................................................342 FIGURE 42 - JTAG PORT INTERFACE TIMING............................................343 FIGURE 43 - 352 PIN ENHANCED BALL GRID ARRAY (SBGA) ..................345
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
LIST OF TABLES TABLE 1 - SBI INTERFACE SIGNALS (30) .....................................................10 TABLE 2 - CLOCK/DATA INTERFACE SIGNALS (15) .....................................16 TABLE 3 - PCI HOST INTERFACE SIGNALS (52) ..........................................18 TABLE 4 - MISCELLANEOUS INTERFACE SIGNALS (160)...........................27 TABLE 5 - PRODUCTION TEST INTERFACE SIGNALS (31) .........................28 TABLE 6 - POWER AND GROUND SIGNALS (64) .........................................30 TABLE 7 - SBI SPE/TRIBUTARY TO RCAS LINK MAPPING ..........................36 TABLE 8 - RECEIVE PACKET DESCRIPTOR FIELDS....................................43 TABLE 9 - RPDRR QUEUE ELEMENT ............................................................49 TABLE 10 - RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS ................................................................................................................51 TABLE 11 - TRANSMIT DESCRIPTOR FIELDS ..............................................61 TABLE 12 - TRANSMIT DESCRIPTOR REFERENCE.....................................67 TABLE 13 - TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS ...................................................................................................69 TABLE 14 - SBI SPE/TRIBUTARY TO TCAS LINK MAPPING.........................77 TABLE 15 - NORMAL MODE PCI HOST ACCESSIBLE REGISTER MEMORY MAP ........................................................................................................81 TABLE 16 - PCI CONFIGURATION REGISTER MEMORY MAP.....................85 TABLE 17 - SPE TYPE CONFIGURATION .................................................... 118 TABLE 18 - FASTCLK FREQUENCY SELECTION........................................ 119 TABLE 19 - SPE TYPE CONFIGURATION ....................................................121 TABLE 20 - FASTCLK FREQUENCY SELECTION........................................121 TABLE 21 - BIG ENDIAN FORMAT................................................................123
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TABLE 22 - LITTLE ENDIAN FORMAT ..........................................................123 TABLE 23 - SBI MODE SPE1 CONFIGURATION..........................................132 TABLE 24 - SBI MODE SPE2 CONFIGURATION..........................................136 TABLE 25 - SBI MODE SPE3 CONFIGURATION..........................................140 TABLE 26 - CRC[1:0] SETTINGS...................................................................150 TABLE 27 - RPQ_RDYN[2:0] SETTINGS ......................................................161 TABLE 28 - RPQ_LFN[1:0] SETTINGS..........................................................162 TABLE 29 - RPQ_SFN[1:0] SETTINGS .........................................................162 TABLE 30 - TDQ_RDYN[2:0] SETTINGS.......................................................196 TABLE 31 - TDQ_FRN[1:0] SETTINGS .........................................................196 TABLE 32 - CRC[1:0] SETTINGS...................................................................224 TABLE 33 - FLAG[2:0] SETTINGS .................................................................230 TABLE 34 - LEVEL[3:0]/TRANS SETTINGS ..................................................232 TABLE 35 - SBI MODE SPE1 CONFIGURATION..........................................248 TABLE 36 - SBI MODE SPE2 CONFIGURATION..........................................252 TABLE 37 - SBI MODE SPE3 CONFIGURATION..........................................256 TABLE 38 - TRIB_TYP ENCODING ...............................................................276 TABLE 39 - TRIB_TYP ENCODING ...............................................................283 TABLE 40 - TEST MODE REGISTER MEMORY MAP ..................................296 TABLE 41 - INSTRUCTION REGISTER ........................................................297 TABLE 42 - BOUNDARY SCAN CHAIN .........................................................298 TABLE 43 - FREEDM-84P672 ABSOLUTE MAXIMUM RATINGS.................333 TABLE 44 - FREEDM-84P672 D.C. CHARACTERISTICS.............................334 TABLE 45 - CLOCKS AND SBI FRAME PULSE (FIGURE 35) ......................336
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TABLE 46 - SBI DROP BUS (FIGURE 36) .....................................................337 TABLE 47 - SBI ADD BUS (FIGURE 37 TO FIGURE 38)...............................338 TABLE 48 - CLOCK/DATA INPUT (FIGURE 39).............................................340 TABLE 49 - CLOCK/DATA OUTPUT (FIGURE 40).........................................340 TABLE 50 - PCI INTERFACE (FIGURE 41) ...................................................341 TABLE 51 - JTAG PORT INTERFACE (FIGURE 42)......................................342 TABLE 52 - FREEDM-84P672 ORDERING INFORMATION..........................344 TABLE 53 - FREEDM-84P672 THERMAL INFORMATION ............................344
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
1
FEATURES * Single-chip multi-channel HDLC controller with a 66 MHz, 32 bit Peripheral Component Interconnect (PCI) Revision 2.1 bus for configuration, monitoring and transfer of packet data, with an on-chip DMA controller with scatter/ gather capabilities. Supports up to 672 bi-directional HDLC channels assigned to a maximum of 84 channelised or unchannelised links conveyed via a Scaleable Bandwidth Interconnect (SBI) interface. Data on the SBI interface is divided into 3 Synchronous Payload Envelopes (SPEs). Each SPE can be configured independently to carry data for either 28 T1/J1 links, 21 E1 links, or 1 unchannelised DS-3 link. Links in a SPE can be configured individually to operate in a clear channel mode, in which case all framing bit locations are assumed to be carrying HDLC data. Links in an SPE can be configured individually to operate in channelised mode, in which case, the number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1 links) and from 1 to 31 (for E1 links). Supports three bi-directional HDLC channels each assigned to an unchannelised link with arbitrary rate link of up to 51.84 MHz when SYSCLK is running at 45 MHz. Each link may be configured individually to replace one of the SPEs conveyed on the SBI interface. For each channel, the HDLC receiver supports programmable flag sequence detection, bit de-stuffing and frame check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame check sequences. For each channel, the receiver checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length. The receiver supports filtering of packets that are larger than a user specified maximum value. Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently to host memory. For channelised links, the octets are aligned with the receive time-slots. For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format.
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
*
For each channel, the HDLC transmitter supports programmable flag sequence generation, bit stuffing and frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows. Supports two levels of non-preemptive packet priority on each transmit channel. Low priority packets will not begin transmission until all high priority packets are transmitted. Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from host memory. For channelised links, the octets are aligned with the transmit time-slots. Provides 32 Kbytes of on-chip memory for partial packet buffering in both the transmit and receive directions. This memory may be configured to support a variety of different channel configurations from a single channel with 32 Kbytes of buffering to 672 channels, each with a minimum of 48 bytes of buffering. Supports PCI burst sizes of up to 256 bytes for transfers of packet data. Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes. Supports 3.3 Volt PCI signaling environment. Supports 3.3 Volt I/O on non-PCI signals. Low power 2.5 Volt 0.25 mm CMOS technology. 352 pin enhanced ball grid array (SBGA) package.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
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APPLICATIONS * * * * * * * IETF PPP interfaces for routers Frame Relay interfaces for ATM or Frame Relay switches and multiplexers FUNI or Frame Relay service inter-working interfaces for ATM switches and multiplexers. Internet/Intranet access equipment. Packet-based DSLAM equipment. Packet over SONET. PPP over SONET.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
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REFERENCES 1. International Organization for Standardization, ISO Standard 3309-1993, "Information Technology - Telecommunications and information exchange between systems - High-level data link control (HDLC) procedures - Frame structure", December 1993. 2. RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering Task Force, July 1994. 3. PCI Special Interest Group, PCI Local Bus Specification, June 1, 1995, Version 2.1. 4. PMC-981125 - "High Density T1/E1 Framer with Integrated VT/TU Mapper and M13 Multiplexer (TEMUX) Data Sheet", PMC-Sierra Inc.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
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APPLICATION EXAMPLES
28xT1
PM8315 TEMUX PM8315 TEMUX PM8315 TEMUX PM7384 FREEDM-84P672
Packet Mem ory PCI Controller / Bus Arbiter
PCI Bus
21xE1
DS3
SBI Bus
PM 5342 SPECTRA-155
PM 5362 TUPP-PLUS
PM 8315 TEM UX PM 8315 TEM UX PM 8315 TEM UX
SB I Bus
OC-3
PM7384 FREEDM-84P672
Packet Mem ory PCI Controller / Bus Arbiter
PCI Bus
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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5
DATA SHEET
PMC-1990445
R STB
FASTCLK SPE1_EN SPE3_EN SPE2_EN REFCLK SYSC LK
C 1FP
BLOCK DIAGRAM
PMC TE S T
C 1FP OUT
ISSUE 5
RCLK[2:0] R D[2:0] SBI P IS O SBI P IS O SBI P IS O Performance Monitor (PMON) Receive C hannel Assigner (RCAS672) Receive HDLC Processor / Partial Packet Buffer (RH DL672) Receive DMA Controller (RMAC 672) PC I Controller (GPIC672) AD [31:0] C/BEB[3:0] PAR
D DATA[7:0] DPL DV5 DDP
SBI Extract
SBI S IP O SBI S IP O SBI S IP O Transm it Channel Assigner (TC AS672) Transmit HDLC Processor / Partial Packet Buffer (THDL672)
ADATA[7:0] APL AV5 ADP AJUST_REQ AACTIVE ADE TEC T[1:0]
SBI Insert
Transm it DMA Controller (TMAC 672)
FRAME B TR D YB IR DYB STO PB DEVSELB ID SEL LOC KB REQB GN TB PER RB SER RB PC IIN TB PC ICLK PC ICLK O M66EN JTAG Port
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE FRAME ENGINE AND DATA LINK MANAGER 84P672
TD O TD I TC K TMS TR S TB
TC LK [2:0] TD[2:0]
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PM7384 FREEDM-84P672
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
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DESCRIPTION The PM7384 FREEDM-84P672 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 672 bi-directional channels. The FREEDM-84P672 may be configured to support channelised T1/J1/E1 or unchannelised DS-3 traffic on up to 84 links conveyed via a Scaleable Bandwidth Interconnect (SBI) interface. The SBI interface transports data in three Synchronous Payload Envelopes (SPEs), each of which may be configured independently to carry either 28 T1/J1 links, 21 E1 links or a single DS-3 link. For channelised T1/J1/E1 links, the FREEDM-84P672 allows up to 672 bidirectional HDLC channels to be assigned to individual time-slots within each independently timed T1/J1 or E1 link. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 24 concatenated timeslots for a T1/J1 link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any particular channel need not be contiguous within a T1/J1 or E1 link. Unchannelised DS-3 links are assigned to a single HDLC channel. Additionally, links may be configured independently to operate in an unframed or "clear channel" mode, in which the bit periods which are normally reserved for framing information in fact carry HDLC data. In unframed mode, links operate as unchannelised (i.e. the entire link is assigned to a single HDLC channel) regardless of link rate. The FREEDM-84P672 supports mixing of channelised T1/J1/E1 and unchannelised or unframed links. The total number of channels in each direction is limited to 672. The maximum possible data rate over all links is 134.208 Mbps (which occurs with three DS-3 links running in unframed mode). The FREEDM-84P672 supports three independently timed bidirectional clock/ data links, each carrying a single unchannellised HDLC stream. The links can be of arbitrary frame format and can operate at up to 51.84 MHz provided SYSCLK is running at 45 MHz. When activated, each link replaces one of the SPEs conveyed on the SBI interface. (The maximum possible data rate when all three clock/data links are activated is 156 Mbps.) In the receive direction, the FREEDM-84P672 performs channel assignment and packet extraction and validation. For each provisioned HDLC channel, the FREEDM-84P672 delineates the packet boundaries using flag sequence detection, and performs bit de-stuffing. Sharing of opening and closing flags, as well as sharing of zeros between flags are supported. The resulting packet data is placed into the internal 32 Kbyte partial packet buffer RAM. The partial packet
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
buffer acts as a logical FIFO for each of the assigned channels. Partial packets are DMA'd out of the RAM, across the PCI bus and into host packet memory. The FREEDM-84P672 validates the frame check sequence for each packet, and verifies that the packet is an integral number of octets in length and is within a programmable minimum and maximum length. The receive packet status is updated before linking the packet into a receive ready queue. The FREEDM84P672 alerts the PCI Host that there are packets in a receive ready queue by, optionally, asserting an interrupt on the PCI bus. Alternatively, in the receive direction, the FREEDM-84P672 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-84P672 directly transfers the received octets into host memory verbatim. If the transparent channel is assigned to a channelised link, then the octets are aligned to the received time-slots. In the transmit direction, the PCI Host provides packets to transmit using a transmit ready queue. For each provisioned HDLC channel, the FREEDM84P672 DMA's partial packets across the PCI bus and into the transmit partial packet buffer. The partial packets are read out of the packet buffer by the FREEDM-84P672 and a frame check sequence is optionally calculated and inserted at the end of each packet. Bit stuffing is performed before being assigned to a particular link. The flag sequence is automatically inserted when there is no packet data for a particular channel. Sequential packets are optionally separated by two flags (an opening flag and a closing flag) or a single flag (combined opening and closing flag). Zeros between flags are not shared. PCI bus latency may cause one or more channels to underflow, in which case, the packets are aborted, and the host is notified. For normal traffic, an abort sequence is generated, followed by inter-frame time fill characters (flags or allones bytes) until a new packet is sourced from the PCI host. No attempt is made to automatically re-transmit an aborted packet. Alternatively, in the transmit direction, the FREEDM-84P672 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-84P672 directly inserts the transmitted octets from host memory. If the transparent channel is assigned to a channelised link, then the octets are aligned to the transmitted time-slots. If a channel underflows due to excessive PCI bus latency, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) to indicate idle channel. Data resumes immediately when the FREEDM-84P672 receives new data from the host. The FREEDM-84P672 is configured, controlled and monitored using the PCI bus interface. The PCI bus supports 3.3 Volt signaling. The FREEDM-84P672 is implemented in low power 2.5 Volt 0.25 mm CMOS technology. All non-PCI FREEDM-84P672 I/O pins are 3.3 volt tolerant. The FREEDM-84P672 is packaged in a 352 pin enhanced ball grid array (SBGA) package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 8
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
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PIN DIAGRAM The FREEDM-84P672 is manufactured in a 352 pin enhanced ball grid array package.
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
VSS
VSS
N.C.
N.C.
N.C.
VDD2V5
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VDD2V5
N.C.
N.C.
N.C.
VSS
VSS
A
B
TA[12]/ VSS VDD3V3 VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VDD2V5 N.C. N.C. N.C. TRS TWRB N.C. TA[10] TA[8] TA[6] VSS VDD3V3 VSS
B
C
N.C.
VSS
VDD3V3
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TRDB
N.C.
N.C.
N.C.
N.C.
VDD3V3
VSS
N.C.
C
D
N.C.
N.C.
N.C.
VDD3V3
N.C.
N.C.
N.C.
N.C.
VDD3V3
N.C.
N.C.
N.C.
VDD3V3
N.C.
N.C.
N.C.
N.C.
VDD3V3
TA[11]
TA[9]
TA[7]
N.C.
VDD3V3
N.C.
TA[5]
N.C.
D
E
N.C.
N.C.
N.C.
N.C.
N.C.
RSTB
TA[4]
N.C.
E
F
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
TA[2]
N.C.
F
G
PCICLKO
N.C.
VDD2V5
N.C.
TA[3]
N.C.
TA[1]
TA[0]
G
H
REQB
N.C.
PCIINTB
N.C.
VDD2V5
N.C.
N.C.
N.C.
H
J
AD[29]
AD[31]
PCICLK
VDD3V3
VDD3V3
N.C.
N.C.
N.C.
J
K
AD[25]
AD[27]
AD[30]
GNTB
N.C.
N.C.
N.C.
N.C.
K
L
N.C.
AD[24]
AD[26]
AD[28]
N.C.
N.C.
N.C.
SYSCLK
L
M
AD[23]
N.C.
IDSEL
CBEB[3]
N.C.
N.C.
N.C.
N.C.
M
N
VSS
VDD2V5
AD[21]
AD[22]
BOTTOM VIEW
VDD3V3
N.C.
N.C.
VSS
N
P
VSS
AD[20]
AD[19]
VDD3V3
VDD2V5
RCLK[2]
N.C.
VSS
P
R
AD[18]
AD[17]
AD[16]
FRAMEB
RD[0]
RD[1]
RCLK[1]
RD[2]
R
T
CBEB[2]
IRDYB
DEVSELB
LOCKB
N.C.
N.C.
N.C.
RCLK[0]
T
U
TRDYB
STOPB
SERRB
AD[15]
TCK
N.C.
N.C.
N.C.
U
V
PERRB
PAR
AD[14]
VDD3V3
VDD3V3
TDI
TRSTB
N.C.
V
W
CBEB[1]
AD[13]
AD[11]
AD[9]
SPE3_EN
N.C.
TDO
TMS
W
Y
AD[12]
AD[10]
AD[8]
AD[6]
TD[1]
VDD2V5
SPE1_EN FASTCLK
Y
AA
VDD2V5
CBEB[0]
AD[5]
AD[2]
C1FP_OUT
TCLK[1]
TD[0]
SPE2_EN
AA
AB
AD[7]
AD[4]
AD[1]
N.C.
AV5
REFCLK
TD[2]
TCLK[0]
AB
AC
TDAT AD[3] AD[0] N.C. VDD3V3 N.C. N.C. N.C. [14] VDD3V3
TDAT N.C. [11] TDAT[7] N.C. VDD3V3
AJUST_REQ
ADATA [7]
DDATA VDD3V3 [4]
DDATA N.C. [1] DDP N.C. VDD3V3 N.C. APL TCLK[2]
AC
AD
TDAT N.C. VSS VDD3V3 N.C. N.C. N.C. N.C. [13] N.C. N.C. N.C. TDAT[6] TDAT[4] TDAT[3]
ADETECT [0]
ADATA N.C. [6]
ADATA [4]
DDATA [2]
ADATA N.C. [1] ADP N.C. VDD3V3 VSS DPL
AD
AE
TDAT VSS VDD3V3 VSS M66EN
PMCTEST
TDAT N.C. [12]
TDAT TDAT[8] [10] N.C. N.C. VDD2V5 N.C. TDAT[2] TDAT[0]
DDATA [7]
DDATA [5]
DDATA [3]
ADATA [2]
DDATA C1FP [0] DV5 VSS VDD3V3 VSS
[15]
AE
AF
VSS
VSS
N.C.
N.C.
N.C.
VDD2V5
N.C.
N.C.
TDAT[9]
N.C.
N.C.
TDAT[5]
VSS
VSS
ADETECT [1]
DDATA TDAT[1] N.C. [6]
ADATA [5]
ADATA VDD2V5 [3]
ADATA AACTIVE [0] N.C. VSS VSS
AF
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
9
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
8
PIN DESCRIPTION Table 1 - SBI Interface Signals (30) Pin Name REFCLK Type Input Pin No. AB3 Function The SBI reference clock signal (REFCLK) provides reference timing for the SBI ADD and DROP busses. REFCLK is nominally a 50% duty cycle clock of frequency 19.44 MHz 50ppm. FASTCLK Input Y1 The high-speed reference clock signal (FASTCLK) is used by the FREEDM-84P672 to generate an internal clock for use when processing DS-3 links. FASTCLK is nominally a 50% duty cycle, 50ppm clock having one of the following frequencies: 51.84 MHz, 44.928 MHz or 66 MHz. C1FP Input AE5 The C1 octet frame pulse signal (C1FP) provides frame synchronisation for devices connected via an SBI interface. C1FP must be asserted for 1 REFCLK cycle every 500 s or multiples thereof (i.e. every 9720 n REFCLK cycles, where n is a positive integer). All devices interconnected via an SBI interface must be synchronised to a C1FP signal from a single source. C1FP is sampled on the rising edge of REFCLK. Note - If the SBI bus is being operated in synchronous mode [Ref. 4], C1FP must be asserted for 1 REFCLK cycle every 6 ms or multiples thereof.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
10
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name C1FPOUT
Type Output
Pin No. AA4
Function The C1 octet frame pulse output signal (C1FPOUT) may be used to provide frame synchronisation for devices interconnected via an SBI interface. C1FPOUT is asserted for 1 REFCLK cycle every 500 s (i.e. every 9720 REFCLK cycles). If C1FPOUT is used for synchronisation, it must be connected to the C1FP inputs of all the devices connected to the SBI interface. C1FPOUT is updated on the rising edge of REFCLK. Note - The C1FPOUT pulse generated by FREEDM-84P672 is not suitable for use in systems in which the SBI bus is operated in synchronous mode [Ref. 4].
DDATA[0] DDATA[1] DDATA[2] DDATA[3] DDATA[4] DDATA[5] DDATA[6] DDATA[7]
Input
AE6 AC8 AD8 AE8 AC10 AE9 AF9 AE10
The SBI DROP bus data signals (DDATA[7:0]) contain the time division multiplexed receive data from the up to 84 independently timed links. Data from each link is transported as a tributary within the SBI TDM bus structure. Multiple PHY devices can drive the SBI DROP bus at uniquely assigned tributary column positions. DDATA[7:0] are sampled on the rising edge of REFCLK.
DDP
Input
AC6
The SBI DROP bus parity signal (DDP) carries the even or odd parity for the DROP bus signals. The parity calculation encompasses the DDATA[7:0], DPL and DV5 signals. Multiple PHY devices can drive DDP at uniquely assigned tributary column positions. This parity signal is intended to detect accidental PHY source clashes in the column assignment. DDP is sampled on the rising edge of REFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
11
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name DPL
Type Input
Pin No. AD1
Function The SBI DROP bus payload signal (DPL) indicates valid data within the SBI TDM bus structure. This signal is asserted during all octets making up a tributary. This signal may be asserted during the V3 or H3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed TDM bus structure. This signal may be deasserted during the octet following the V3 or H3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed TDMBUS structure. Multiple PHY devices can drive DPL at uniquely assigned tributary column positions. DPL is sampled on the rising edge of REFCLK.
DV5
Input
AE4
The SBI DROP bus payload indicator signal (DV5) locates the position of the floating payloads for each tributary within the SBI TDM bus structure. Timing differences between the port timing and the TDM bus timing are indicated by adjustments of this payload indicator relative to the fixed TDM bus structure. Multiple PHY devices can drive DV5 at uniquely assigned tributary column positions. All movements indicated by this signal must be accompanied by appropriate adjustments in the DPL signal. DV5 is sampled on the rising edge of REFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
12
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name ADATA[0] ADATA[1] ADATA[2] ADATA[3] ADATA[4] ADATA[5] ADATA[6] ADATA[7]
Type Tristat e Output
Pin No. AF5 AD7 AE7 AF7 AD9 AF8 AD10 AC11
Function The SBI ADD bus data signals (ADATA[7:0]) contain the time division multiplexed transmit data from the up to 84 independently timed links. Data from each link is transported as a tributary within the SBI TDM bus structure. Multiple link layer devices can drive the SBI ADD bus at uniquely assigned tributary column positions. ADATA[7:0] are tristated when the FREEDM-84P672 is not outputting data on a particular tributary column. ADATA[7:0] are updated on the rising edge of REFCLK.
ADP
Tristat e Output
AD5
The SBI ADD bus parity signal (ADP) carries the even or odd parity for the ADD bus signals. The parity calculation encompasses the ADATA[7:0], APL and AV5 signals. Multiple link layer devices can drive this signal at uniquely assigned tributary column positions. ADP is tristated when the FREEDM-84P672 is not outputting data on a particular tributary column. This parity signal is intended to detect accidental link layer source clashes in the column assignment. ADP is updated on the rising edge of REFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
13
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name APL
Type Tristat e Output
Pin No. AC2
Function The SBI ADD bus payload signal (APL) indicates valid data within the SBI TDM bus structure. This signal is asserted during all octets making up a tributary. This signal may be asserted during the V3 or H3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed TDM bus structure. This signal may be deasserted during the octet following the V3 or H3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed TDMBUS structure. Multiple link layer devices can drive this signal at uniquely assigned tributary column positions. APL is tristated when the FREEDM-84P672 is not outputting data on a particular tributary column. APL is updated on the rising edge of REFCLK.
AV5
Tristat e output
AB4
The SBI ADD bus payload indicator signal (AV5) locates the position of the floating payloads for each tributary within the SBI TDM bus structure. Timing differences between the port timing and the TDM bus timing are indicated by adjustments of this payload indicator relative to the fixed TDM bus structure. Multiple link layer devices can drive this signal at uniquely assigned tributary column positions. APL is tristated when the FREEDM-84P672 is not outputting data on a particular tributary column. All movements indicated by this signal are accompanied by appropriate adjustments in the APL signal. AV5 is updated on the rising edge of REFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
14
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name AJUST_REQ
Type Input
Pin No. AC12
Function The SBI ADD bus justification request signal (AJUST_REQ) is used to speed up or slow down the output data rate of the FREEDM84P672. Negative timing adjustments are requested by asserting AJUST_REQ during the V3 or H3 octet, depending on the tributary type. In response to this the FREEDM-84P672 will send an extra byte in the V3 or H3 octet of the next frame along with a valid APL indicating a negative justification. Positive timing adjustments are requested by asserting AJUST_REQ during the octet following the V3 or H3 octet, depending on the tributary type. FREEDM-84P672 will respond to this by not sending an octet during the octet following the V3 or H3 octet of the next frame and deasserting APL to indicate a positive justification. AJUST_REQ is sampled on the rising edge of REFCLK.
AACTIVE
Output
AF4
The SBI ADD bus active indicator signal (AACTIVE) is asserted whenever FREEDM84P672 is driving the SBI ADD bus signals, ADATA[7:0], ADP, APL and AV5. All other Link Layer devices driving the SBI ADD bus should listen to this signal (to detect multiple sources accidentaly driving the bus) and should cease driving the bus whenever a conflict is detected. AACTIVE is updated on the rising edge of REFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
15
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name ADETECT[0] ADETECT[1]
Type Input
Pin No. AD12 AF12
Function The SBI ADD bus conflict detection signals (ADETECT[1:0]) may be connected to the AACTIVE outputs of other link layer devices sharing the SBI ADD bus. FREEDM-84P672 will immediately tristate the SBI ADD bus signals ADATA[7:0], ADP, APL and AV5 if either of ADETECT[1] and ADETECT[0] is asserted. ADETECT[1:0] are asynchronous inputs.
Table 2 - Clock/Data Interface Signals (15) Pin Name RCLK[0] RCLK[1] RCLK[2] Type Input Pin No. T1 R2 P3 Function The receive line clock signals (RCLK[2:0]) contain the recovered line clock for the 3 independently timed links. RCLK[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e. not part of the HDLC packet). RCLK[2:0] is nominally a 50% duty cycle clock between 0 and 51.84 MHz. The RCLK[n] inputs are invalid and should be tied low when their associated link is not configured for operation (i.e. SPEn_EN input is high). RD[0] RD[1] RD[2] Input R4 R3 R1 The receive data signals (RD[2:0]) contain the recovered line data for the 3 independently timed links. RD[2:0] contain HDLC packet data. For certain transmission formats, RD[2:0] may contain place holder bits or timeslots. RCLK[n] must be externally gapped during the place holder positions in the RD[n] stream. The FREEDM-84P672 supports a maximum data rate of 51.84 Mbit/s on each link. RD[2:0] are sampled on the rising edge of the corresponding RCLK[2:0].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
16
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name TCLK[0] TCLK[1] TCLK[2]
Type Input
Pin No. AB1 AA3 AC1
Function The transmit line clock signals (TCLK[2:0]) contain the transmit clocks for the 3 independently timed links. TCLK[n] must be externally gapped during the bits or time-slots that are not part of the transmission format payload (i.e. not part of the HDLC packet). TCLK[2:0] is nominally a 50% duty cycle clock between 0 and 51.84 MHz. The TCLK[n] inputs are invalid and should be tied low when their associated link is not configured for operation (i.e. SPEn_EN input is high).
TD[0] TD[1] TD[2]
Output
AA2 Y4 AB2
The transmit data signals (TD[2:0]) contain the transmit data for the 3 independently timed links. TD[2:0] contain HDLC packet data. For certain transmission formats, TD[2:0] may contain place holder bits or timeslots. TCLK[n] must be externally gapped during the place holder positions in the TD[n] stream. The FREEDM-84P672 supports a maximum data rate of 51.84 Mbit/s on each link. TD[2:0] are updated on the falling edge of the corresponding TCLK[2:0] clock.
SPE1_EN SPE2_EN SPE3_EN
Input
Y2 AA1 W4
The Synchronous Payload Envelope Enable signals (SPEn_EN) configure the operation of the clock/data inputs and the SBI Interface. When SPEn_EN is low, the corresponding Synchronous Payload Envelope conveyed on the SBI interface is unused and the corresponding independently timed link (signals RCLK[n-1], RD[n-1], TCLK[n-1] and TD[n-1]) is enabled. When SPEn_EN is high, the corresponding Synchronous Payload Envelope conveyed on the SBI interface is enabled and the corresponding independently timed link is disabled. SPEn_EN are asynchronous inputs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
17
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Table 3 - PCI Host Interface Signals (52) Pin Name PCICLK Type Input Pin No. J24 Function The PCI clock signal (PCICLK) provides timing for PCI bus accesses. PCICLK is a nominally 50% duty cycle, 25 to 66 MHz clock. The PCI clock output signal (PCICLKO) is a buffered version of the PCICLK. PCICLKO may be used to derive the SYSCLK input. The PCI bus command and byte enable bus (C/BEB[3:0]) contains the bus command or the byte valid indications. During the first clock cycle of a transaction, C/BEB[3:0] contains the bus command code. For subsequent clock cycles, C/BEB[3:0] identifies which bytes on the AD[31:0] bus carry valid data. C/BEB[3] is associated with byte 3 (AD[31:24]) while C/BEB[0] is associated with byte 0 (AD[7:0]). When C/BEB[n] is set high, the associated byte is invalid. When C/BEB[n] is set low, the associated byte is valid. When the FREEDM-84P672 is the initiator, C/BEB[3:0] is an output bus. When the FREEDM-84P672 is the target, C/BEB[3:0] is an input bus. When the FREEDM-84P672 is not involved in the current transaction, C/BEB[3:0] is tristated. As an output bus, C/BEB[3:0] is updated on the rising edge of PCICLK. As an input bus, C/BEB[3:0] is sampled on the rising edge of PCICLK.
PCICLKO
Output
G26
C/BEB[0] C/BEB[1] C/BEB[2] C/BEB[3]
I/O
AA25 W26 T26 M23
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
18
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31]
Type I/O
Pin No. AC25 AB24 AA23 AC26 AB25 AA24 Y23 AB26 Y24 W23 Y25 W24 Y26 W25 V24 U23 R24 R25 R26 P24 P25 N24 N23 M26 L25 K26 L24 K25 L23 J26 K24 J25
Function The PCI address and data bus (AD[31:0]) carries the PCI bus multiplexed address and data. During the first clock cycle of a transaction, AD[31:0] contains a physical byte address. During subsequent clock cycles of a transaction, AD[31:0] contains data. A transaction is defined as an address phase followed by one or more data phases. When Little-Endian byte formatting is selected, AD[31:24] contain the most significant byte of a DWORD while AD[7:0] contain the least significant byte. When Big-Endian byte formatting is selected. AD[7:0] contain the most significant byte of a DWORD while AD[31:24] contain the least significant byte. When the FREEDM-84P672 is the initiator, AD[31:0] is an output bus during the first (address) phase of a transaction. For write transactions, AD[31:0] remains an output bus for the data phases of the transaction. For read transactions, AD[31:0] is an input bus during the data phases. When the FREEDM-84P672 is the target, AD[31:0] is an input bus during the first (address) phase of a transaction. For write transactions, AD[31:0] remains an input bus during the data phases of the transaction. For read transactions, AD[31:0] is an output bus during the data phases. When the FREEDM-84P672 is not involved in the current transaction, AD[31:0] is tristated. As an output bus, AD[31:0] is updated on the rising edge of PCICLK. As an input bus, AD[31:0] is sampled on the rising edge of PCICLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
19
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name PAR
Type I/O
Pin No. V25
Function The parity signal (PAR) indicates the parity of the AD[31:0] and C/BEB[3:0] buses. Even parity is calculated over all 36 signals in the buses regardless of whether any or all the bytes on the AD[31:0] are valid. PAR always reports the parity of the previous PCICLK cycle. Parity errors detected by the FREEDM-84P672 are indicated on output PERRB and in the FREEDM-84P672 Interrupt Status register. When the FREEDM-84P672 is the initiator, PAR is an output for writes and an input for reads. When the FREEDM-84P672 is the target, PAR is an input for writes and an output for reads. When the FREEDM-84P672 is not involved in the current transaction, PAR is tristated. As an output signal, PAR is updated on the rising edge of PCICLK. As an input signal, PAR is sampled on the rising edge of PCICLK.
FRAMEB
I/O
R23
The active low cycle frame signal (FRAMEB) identifies a transaction cycle. When FRAMEB transitions low, the start of a bus transaction is indicated. FRAMEB remains low to define the duration of the cycle. When FRAMEB transitions high, the last data phase of the current transaction is indicated. When the FREEDM-84P672 is the initiator, FRAMEB is an output. When the FREEDM-84P672 is the target, FRAMEB is an input. When the FREEDM-84P672 is not involved in the current transaction, FRAMEB is tristated. As an output signal, FRAMEB is updated on the rising edge of PCICLK. As an input signal, FRAMEB is sampled on the rising edge of PCICLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
20
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name TRDYB
Type I/O
Pin No. U26
Function The active low target ready signal (TRDYB) indicates when the target is ready to start or continue with a transaction. TRDYB works in conjunction with IRDYB to complete transaction data phases. During a transaction in progress, TRDYB is set high to indicate that the target cannot complete the current data phase and to force a wait state. TRDYB is set low to indicate that the target can complete the current data phase. The data phase is completed when TRDYB is set low and the initiator ready signal (IRDYB) is also set low. When the FREEDM-84P672 is the initiator, TRDYB is an input. When the FREEDM-84P672 is the target, TRDYB is an output. During accesses to FREEDM-84P672 registers, TRDYB is set high to extend data phases over multiple PCICLK cycles. When the FREEDM-84P672 is not involved in the current transaction, TRDYB is tristated. As an output signal, TRDYB is updated on the rising edge of PCICLK. As an input signal, TRDYB is sampled on the rising edge of PCICLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
21
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name IRDYB
Type I/O
Pin No. T25
Function The active low initiator ready (IRDYB) signal is used to indicate whether the initiator is ready to start or continue with a transaction. IRDYB works in conjunction with TRDYB to complete transaction data phases. When IRDYB is set high and a transaction is in progress, the initiator is indicating it cannot complete the current data phase and is forcing a wait state. When IRDYB is set low and a transaction is in progress, the initiator is indicating it has completed the current data phase. The data phase is completed when IRDYB is set low and the target ready signal (IRDYB) is also set low. When the FREEDM-84P672 is the initiator, IRDYB is an output. When the FREEDM-84P672 is the target, IRDYB is an input. When the FREEDM-84P672 is not involved in the current transaction, IRDYB is tristated. IRDYB is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
22
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name STOPB
Type I/O
Pin No. U25
Function The active low stop signal (STOPB) requests the initiator to stop the current bus transaction. When STOPB is set high by a target, the initiator continues with the transaction. When STOPB is set low, the initiator will stop the current transaction. When the FREEDM-84P672 is the initiator, STOPB is an input. When STOPB is sampled low, the FREEDM-84P672 will terminate the current transaction in the next PCICLK cycle. When the FREEDM-84P672 is the target, STOPB is an output. The FREEDM-84P672 only issues transaction stop requests when responding to reads and writes to configuration space (disconnecting after 1 DWORD transferred) or if an initiator introduces wait states during a transaction. When the FREEDM-84P672 is not involved in the current transaction, STOPB is tristated. STOPB is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input.
IDSEL
Input
M24
The initialization device select signal (IDSEL) enables read and write access to the PCI configuration registers. When IDSEL is set high during the address phase of a transaction and the C/BEB[3:0] code indicates a register read or write, the FREEDM-84P672 performs a PCI configuration register transaction and asserts the DEVSELB signal in the next PCICLK period. IDSEL is sampled on the rising edge of PCICLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
23
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name DEVSELB
Type I/O
Pin No. T24
Function The active low device select signal (DEVSELB) indicates that a target claims the current bus transaction. During the address phase of a transaction, all targets decode the address on the AD[31:0] bus. When a target, recognizes the address as its own, it sets DEVSELB low to indicate to the initiator that the address is valid. If no target claims the address in six bus clock cycles, the initiator assumes that the target does not exist or cannot respond and aborts the transaction. When the FREEDM-84P672 is the initiator, DEVSELB is an input. If no target responds to an address in six PCICLK cycles, the FREEDM84P672 will abort the current transaction and alerts the PCI Host via an interrupt. When the FREEDM-84P672 is the target, DEVSELB is an output. DELSELB is set low when the address on AD[31:0] is recognised. When the FREEDM-84P672 is not involved in the current transaction, DEVSELB is tristated. FREEDM-84P672 is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input.
LOCKB
Input
T23
The active low bus lock signal (LOCKB) locks a target device. When LOCKB and FRAME are set low, and the FREEDM-84P672 is the target, an initiator is locking the FREEDM-84P672 as an "owned" target. Under these circumstances, the FREEDM-84P672 will reject all transaction with other initiators. The FREEDM-84P672 will continue to reject other initiators until its owner releases the lock by forcing both FRAMEB and LOCKB high. As a initiator, the FREEDM84P672 will never lock a target. LOCKB is sampled using the rising edge of PCICLK.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name REQB
Type Tristate Output
Pin No. H26
Function The active low PCI bus request signal (REQB) requests an external arbiter for control of the PCI bus. REQB is set low when the FREEDM84P672 desires access to the host memory. REQB is set high when access is not desired. REQB is updated on the rising edge of PCICLK. The active low PCI bus grant signal (GNTB) indicates the granting of control over the PCI in response to a bus request via the REQB output. When GNTB is set high, the FREEDM-84P672 does not have control over the PCI bus. When GNTB is set low, the external arbiter has granted the FREEDM-84P672 control over the PCI bus. However, the FREEDM-84P672 will not proceed until the FRAMEB signal is sampled high, indicating no current transactions are in progress. GNTB is sampled on the rising edge of PCICLK. The active low PCI interrupt signal (PCIINTB) is set low when a FREEDM-84P672 interrupt source is active, and that source is unmasked. The FREEDM-84P672 may be enabled to report many alarms or events via interrupts. PCIINTB returns high when the interrupt is acknowledged via an appropriate register access. PCIINTB is an open drain output and is asynchronous to PCICLK.
GNTB
Input
K23
PCIINTB
OD Output
H24
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name PERRB
Type I/O
Pin No. V26
Function The active low parity error signal (PERRB) indicates a parity error over the AD[31:0] and C/BEB[3:0] buses. Parity error is signalled when even parity calculations do not match the PAR signal. PERRB is set low at the cycle immediately following an offending PAR cycle. PERRB is set high when no parity error is detected. PERRB is enabled by setting the PERREN bit in the Control/Status register in the PCI Configuration registers space. Regardless of the setting of PERREN, parity errors are always reported by the PERR bit in the Control/Status register in the PCI Configuration registers space. PERRB is updated on the rising edge of PCICLK.
SERRB
OD Output
U24
The active low system error signal (SERRB) indicates an address parity error. Address parity errors are detected when the even parity calculations during the address phase do not match the PAR signal. When the FREEDM84P672 detects a system error, SERRB is set low for one PCICLK period. SERRB is enabled by setting the SERREN bit in the Control/Status register in the PCI Configuration registers space. Regardless of the setting of SERREN, parity errors are always reported by the SERR bit in the Control/Status register in the PCI Configuration registers space. SERRB is an open drain output and is updated on the rising edge of PCICLK.
M66EN
Input
AE23
The active high 66 MHz mode enable signal (M66EN) reflects the speed of operation of the PCI bus. M66EN should be set high for 66 MHz operation on the PCI bus. M66EN should be set low for 33 MHz operation on the PCI bus.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Table 4 - Miscellaneous Interface Signals (160) Pin Name SYSCLK Type Input Pin No. L1 Function The system clock (SYSCLK) provides timing for the core logic. SYSCLK is nominally a 50% duty cycle clock of frequency 45 MHz 50ppm. The active low reset signal (RSTB) signal provides an asynchronous FREEDM-84P672 reset. RSTB is an asynchronous input. When RSTB is set low, all FREEDM-84P672 registers are forced to their default states. In addition, all SBI and PCI output pins are forced tristate and will remain tristated until RSTB is set high.
RSTB
Input
E3
PMCTEST
Input
AE22 The PMC production test enable signal (PMCTEST) places the FREEDM-84P672 is test mode. When PMCTEST is set high, production test vectors can be executed to verify manufacturing via the test mode interface signals TA[11:0], TA[12]/TRS, TRDB, TWRB and TDAT[15:0]. PMCTEST must be tied low for normal operation. U4 The test clock signal (TCK) provides timing for test operations that can be carried out using the IEEE P1149.1 test access port. TMS and TDI are sampled on the rising edge of TCK. TDO is updated on the falling edge of TCK. The test mode select signal (TMS) controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor. The test data input signal (TDI) carries test data into the FREEDM-84P672 via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor.
TCK
Input
TMS
Input
W1
TDI
Input
V3
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name TDO
Type
Pin No.
Function The test data output signal (TDO) carries test data out of the FREEDM-84P672 via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output which is inactive except when scanning of data is in progress. The active low test reset signal (TRSTB) provides an asynchronous FREEDM-84P672 test access port reset via the IEEE P1149.1 test access port. TRSTB is an asynchronous input with an integral pull up resistor. Note that when TRSTB is not being used, it must be connected to the RSTB input.
Tristate W2 Output
TRSTB
Input
V2
NC1-152
Open
These pins must be left unconnected.
Table 5 - Production Test Interface Signals (31) Pin Name TA[0] TA[1] TA[2] TA[3] TA[4] TA[5] TA[6] TA[7] TA[8] TA[9] TA[10] TA[11] TA[12]/TR S Type Input Pin No. G1 G2 F2 G4 E2 D2 B4 D6 B5 D7 B6 D8 B9 Function The test mode address bus (TA[11:0]) selects specific registers during production test (PMCTEST set high) read and write accesses. In normal operation (PMCTEST set low), these signals should be grounded.
Input
The test register select signal (TA[12]/TRS) selects between normal and test mode register accesses during production test (PMCTEST set high). TRS is set high to select test registers and is set low to select normal registers. In normal operation (PMCTEST set low), this signal should be grounded.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name TRDB
Type Input
Pin No. C8
Function The test mode read enable signal (TRDB) is set low during FREEDM-84P672 register read accesses during production test (PMCTEST set high). The FREEDM-84P672 drives the test data bus (TDAT[15:0]) with the contents of the addressed register while TRDB is low. In normal operation (PMCTEST set low), this signal should be tied to logic 1. The test mode write enable signal (TWRB) is set low during FREEDM-84P672 register write accesses during production test (PMCTEST set high). The contents of the test data bus (TDAT[15:0]) are clocked into the addressed register on the rising edge of TWRB. In normal operation (PMCTEST set low), this signal should be tied to logic 1. The bi-directional test mode data bus (TDAT[15:0]) carries data read from or written to FREEDM-84P672 registers during production test (PMCTEST set high). In normal operation (PMCTEST set low), these signals should be left unconnected.
TWRB
Input
B8
TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15]
I/O
AE11 AF11 AE12 AD13 AD14 AF15 AD15 AC15 AE17 AF18 AE18 AC17 AE19 AD19 AC19 AE21
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Table 6 - Power and Ground Signals (64) Pin Name VDD3V3[1] VDD3V3[2] VDD3V3[3] VDD3V3[4] VDD3V3[5] VDD3V3[6] VDD3V3[7] VDD3V3[8] VDD3V3[9] VDD3V3[10] VDD3V3[11] VDD3V3[12] VDD3V3[13] VDD3V3[14] VDD3V3[15] VDD3V3[16] VDD3V3[17] VDD3V3[18] VDD3V3[19] VDD3V3[20] VDD3V3[21] VDD3V3[22] VDD3V3[23] VDD3V3[24] VDD2V5[1] VDD2V5[2] VDD2V5[3] VDD2V5[4] VDD2V5[5] VDD2V5[6] VDD2V5[7] VDD2V5[8] VDD2V5[9] VDD2V5[10] VDD2V5[11] VDD2V5[12] Type Power Pin No. B25 C3 C24 D4 D9 D14 D18 D23 J4 N4 P23 J23 V4 V23 AC4 AC9 AC13 AC18 AC23 AD3 AE2 AE25 B2 AD24 H4 P4 Y3 AF6 AE14 AF21 AA26 N25 G24 A21 B13 A6 Function The VDD3V3[24:1] DC power pins should be connected to a well decoupled +3.3 V DC supply. These power pins provide DC current to the I/O pads.
Power
The VDD2V5[12:1] DC power pins should be connected to a well decoupled +2.5 V DC supply. These power pins provide DC current to the digital core.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Pin Name VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28]
Type Ground
Pin No. A1 A2 A13 A14 A25 A26 B1 B3 B24 B26 C2 C25 N1 N26 P1 P26 AD2 AD25 AE1 AE3 AE24 AE26 AF1 AF2 AF13 AF14 AF25 AF26
Function The VSS[28:1] DC ground pins should be connected to ground. They provide a ground reference for the 3.3 V rail. They also provide a ground reference for the 2.5 V rail.
Notes on Pin Description: 1. All FREEDM-84P672 non-PCI inputs and bi-directionals present minimum capacitive loading and are 3.3 Volt tolerant. PCI signals conform to the 3.3 Volt signaling environment. 2. All FREEDM-84P672 non-PCI outputs and bi-directionals have 8 mA drive capability, except the TDO output which has 4 mA drive capability. 3. All FREEDM-84P672 outputs can be tristated under control of the IEEE P1149.1 test access port, even those which do not tristate under normal operation. All non-PCI outputs and bi-directionals are 3.3 V tolerant when tristated.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
4. All non-PCI inputs are Schmitt triggered. Inputs TMS, TDI and TRSTB have internal pull-up resistors. 5. Power to the VDD3V3 pins should be applied before power to the VDD2V5 pins is applied. Similarly, power to the VDD2V5 pins should be removed before power to the VDD3V3 pins is removed.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
9 9.1
FUNCTIONAL DESCRIPTION Scaleable Bandwidth Interconnect (SBI) Interface The Scaleable Bandwidth Interconnect is a synchronous, time-division multiplexed bus designed to transfer, in a pin-efficient manner, data belonging to a number of independently timed links of varying bandwidth. The bus is timed to a reference 19.44MHz clock and a 2kHz or 166.7Hz frame pulse. All sources and sinks of data on the bus are timed to the reference clock and frame pulse. Timing is communicated across the Scaleable Bandwidth Interconnect by floating data structures. Payload indicator signals in the SBI control the position of the floating data structure and therefore the timing. When sources are running faster than the SBI the floating payload structure is advanced by an octet be passing an extra octet in the V3 octet locations (H3 octet for DS3 mappings). When the source is slower than the SBI the floating payload is retarded by leaving the octet after the V3 or H3 octet unused. Both these rate adjustments are indicated by the SBI control signals. An SBI interface consists of a DROP BUS and an ADD BUS. On the DROP BUS all timing is sourced from the PHY and is passed onto the FREEDM-84P672 by the arrival rate of data over the SBI. On the ADD BUS timing can be controlled by either the PHY or the FREEDM-84P672. When the FREEDM-84P672 is the timing master the PHY device determines its transmit timing information from the arrival rate of data across the SBI. When the PHY device is the timing master it signals the FREEDM-84P672 to speed up or slow down with justification request signals. The PHY timing master indicates a speedup request to the Link Layer by asserting the justification request signal high during the V3 or H3 octet. When this is detected by the FREEDM-84P672 it will advance the channel by inserting data in the next V3 or H3 octet as described above. The PHY timing master indicates a slowdown request to the FREEDM-84P672 by asserting the justification request signal high during the octet after the V3 or H3 octet. The FREEDM-84P672 responds by leaving the octet following the next V3 or H3 octet unused. Both advance and retard rate adjustments take place in the frame or multi-frame following the justification request. The SBI multiplexing structure is modeled on the SONET/SDH standards. The SONET/SDH virtual tributary structure is used to carry T1/J1 and E1 links. Unchannelized DS3 payloads follow a byte synchronous structure modeled on the SONET/SDH format. The SBI structure uses a locked SONET/SDH structure fixing the position of the TUG-3/TU-3 relative to the STS-3/STM-1 transport frame. The SBI is also of fixed frequency and alignment as determined by the reference clock (REFCLK)
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
and frame indicator signal (C1FP). Frequency deviations are compensated by adjusting the location of the T1/J1/E1/DS3 channels using floating tributaries as determined by the V5 indicator and payload signals (DV5, AV5, DPL and APL). The multiplexed links are separated into three Synchronous Payload Envelopes. Each envelope may be configured independently to carry up to 28 T1/J1s, 21 E1s or a DS3. 9.2 High-Level Data Link Control (HDLC) Protocol Figure 1 shows a diagram of the synchronous HDLC protocol supported by the FREEDM-84P672 device. The incoming stream is examined for flag bytes (01111110 bit pattern) which delineate the opening and closing of the HDLC packet. The packet is bit de-stuffed which discards a "0" bit which directly follows five contiguous "1" bits. The resulting HDLC packet size must be a multiple of an octet (8 bits) and within the expected minimum and maximum packet length limits. The minimum packet length is that of a packet containing two information bytes (address and control) and FCS bytes. For packets with CRC-CCITT as FCS, the minimum packet length is four bytes while those with CRC-32 as FCS, the minimum length is six bytes. An HDLC packet is aborted when seven contiguous "1" bits (with no inserted "0" bits) are received. At least one flag byte must exist between HDLC packets for delineation. Contiguous flag bytes, or all ones bytes between packets are used as an "inter-frame time fill". Adjacent flag bytes may share zeros. Figure 1 - HDLC Frame
Flag Information HDLC Packet FCS Flag Flag
The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. Figure 2 shows a CRC encoder block diagram using the generating polynomial g(X) = 1 + g1X + g2X2 +...+ gn-1Xn-1 + Xn. The CRC-CCITT FCS is two bytes in size and has a generating polynomial g(X) = 1 + X5 + X12 + X16. The CRC-32 FCS is four bytes in size and has a generating polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22 + X23 + X26 + X32. The first FCS bit received is the residue of the highest term.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Figure 2 - CRC Generator
g1 D0 D1
g2 D2
gn-1 Dn-1 Message
LSB
Parity Check Digits
MSB
9.3
SBI Extracter and PISO The SBI receive circuitry consists of an SBI Extract block and three SBI Parallel to Serial Converter (SBI PISO) blocks. The SBI Extract block receives data from the SBI DROP BUS and converts it to an internal parallel bus format. The received data is then converted to serial bit streams by the PISO blocks. Each PISO block processes one of the three Synchronous Payload Envelopes (SPEs) conveyed on the SBI DROP BUS. The SBI Extract block may be configured to enable or disable reception of individual triburaries within the SBI DROP bus. Individual triburaries may also be configured to operate in framed or unframed mode. Each PISO block inputs data related to one SPE from the internal parallel bus and generates either 28 serial data streams at T1/J1 rate, 21 streams at E1 rate or a single stream at DS-3 rate. These serial streams are then processed by the Receive Channel Assigner block.
9.4
Receive Channel Assigner The Receive Channel Assigner block (RCAS672) processes up to 84 serial links. When receiving data from the SBI PISO blocks, links may be configured to support channelised T1/J1/E1 traffic, unchannelised DS-3 traffic or unframed traffic at T1/J1, E1 or DS-3 rates. When receiving data from the RCLK/RD inputs, links 0, 1 and 2 support unchannelised data at arbitary rates up to 51.84 Mbps. Each link is independent and has its own associated clock. For each link, the RCAS672 performs a serial to parallel conversion to form data bytes. The data bytes are multiplexed, in byte serial format, for delivery to the Receive HDLC Processor / Partial Packet Buffer block (RHDL672) at SYSCLK rate. In the event
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
where multiple streams have accumulated a byte of data, multiplexing is performed on a fixed priority basis with link #0 having the highest priority and link #83 the lowest. The 84 RCAS links have a fixed relationship to the SPE and tributary numbers on the SBI DROP BUS as shown in the following table. Table 7 - SBI SPE/Tributary to RCAS Link Mapping SBI SPE No. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SBI Trib. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 RCAS Link No. 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 SBI SPE No. 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SBI Trib. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 RCAS Link No. 1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 SBI SPE No. 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 SBI Trib. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 RCAS Link No. 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SBI SPE No. 1 1 1 1 1 1
SBI Trib. No. 23 24 25 26 27 28
RCAS Link No. 66 69 72 75 78 81
SBI SPE No. 2 2 2 2 2 2
SBI Trib. No. 23 24 25 26 27 28
RCAS Link No. 67 70 73 76 79 82
SBI SPE No. 3 3 3 3 3 3
SBI Trib. No. 23 24 25 26 27 28
RCAS Link No. 68 71 74 77 80 83
Links containing a T1/J1 or an E1 stream may be channelised. Data at each time-slot may be independently assigned to a different channel. The RCAS672 performs a table lookup to associate the link and time-slot identity with a channel. The position of T1/J1 and E1 framing bits/bytes is identified by frame pulse signals generated by the SBI PISO blocks. Links containing a DS-3 stream are unchannelised, i.e. all data on the link belongs to one channel. The RCAS672 performs a table lookup using only the link number to determine the associated channel, as time-slots are non-existent in unchannelised links. Links may additionally be configured to operate in an unframed "clear channel" mode, in which all bit positions, including those normally reserved for framing information, are assumed to be carrying HDLC data. Links so configured operate as unchannelised regardless of link rate and the RCAS672 performs a table lookup using only the link number to determine the associated channel. 9.4.1 Line Interface There are 84 line interface blocks in the RCAS672. Each line interface block contains a bit counter, an 8-bit shift register and a holding register that, together, perform serial to parallel conversion. Whenever the holding register is updated, a request for service is sent to the priority encoder block. When acknowledged by the priority encoder, the line interface responds with the data residing in the holding register. To support channelised links, each line interface block contains a time-slot counter. The time-slot counter is incremented each time the holding register is updated and is reset on detection of a frame pulse from the SBI PISO blocks. For unchannelised or unframed links, the time-slot counter is held reset.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
9.4.2 Priority Encoder The priority encoder monitors the line interfaces for requests and synchronises them to the SYSCLK timing domain. Requests are serviced on a fixed priority scheme where highest to lowest priority is assigned from the line interface attached to link 0 to that attached to link 83. Thus, simultaneous requests from link `m' will be serviced ahead of link `n', if m < n. When there are no pending requests, the priority encoder generates an idle cycle. In addition, once every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests are serviced. This cycle is used by the channel assigner downstream for host microprocessor accesses to the provisioning RAMs. 9.4.3 Channel Assigner The channel assigner block determines the channel number of the data byte currently being processed. The block contains a 2688 word channel provision RAM. The address of the RAM is constructed from concatenating the link number and the time-slot number of the current data byte. The fields of each RAM word include the channel number and a time-slot enable flag. The time-slot enable flag labels the current time-slot as belonging to the channel indicted by the channel number field. 9.4.4 Loopback Controller The loopback controller block implements the channel based diagnostic loopback function. Every valid data byte belonging to a channel with diagnostic loopback enabled from the Transmit HDLC Processor / Partial Packet Buffer block (THDL672) is written into a 256 word FIFO. The loopback controller monitors for an idle time-slot or a time-slot carrying a channel with diagnostic loopback enabled. If either conditions hold, the current data byte is replaced by data retrieved from the loopback data FIFO. 9.5 Receive HDLC Processor / Partial Packet Buffer The Receive HDLC Processor / Partial Packet Buffer block (RHDL672) processes up to 672 synchronous transmission HDLC data streams. Each channel can be individually configured to perform flag sequence detection, bit de-stuffing and CRC-CCITT or CRC-32 verification. The packet data is written into the partial packet buffer. At the end of a frame, packet status including CRC error, octet alignment error and maximum length violation are also loaded into the partial packet buffer. Alternatively, a channel can be provisioned as transparent, in which case, the HDLC data stream is passed to the partial packet buffer processor verbatim.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
There is a natural precedence in the alarms detectable on a receive packet. Once a packet exceeds the programmable maximum packet length, no further processing is performed on it. Thus, octet alignment detection, FCS verification and abort recognition are squelched on packets with a maximum length violation. An abort indication squelches octet alignment detection, minimum packet length violations, and FCS verification. In addition, FCS verification is only performed on packets that do not have octet alignment errors, in order to allow the RHDL672 to perform CRC calculations on a byte-basis. The partial packet buffer is an 32 Kbyte RAM that is divided into 16-byte blocks. Each block has an associated pointer which points to another block. A logical FIFO is created for each provisioned channel by programming the block pointers to form a circular linked list. A channel FIFO can be assigned a minimum of 3 blocks (48 bytes) and a maximum of 2048 blocks (32 Kbytes). The depth of the channel FIFOs are monitored in a round-robin fashion. Requests are made to the Receive DMA Controller block (RMAC672) to transfer, to the PCI host memory, data in channel FIFOs with depths exceeding their associated threshold. 9.5.1 HDLC Processor The HDLC processor is a time-slice state machine which can process up to 672 independent channels. The state vector and provisioning information for each channel is stored in a RAM. Whenever new channel data arrives, the appropriate state vector is read from the RAM, processed and written back to the RAM. The HDLC state-machine can be configured to perform flag delineation, bit de-stuffing, CRC verification and length monitoring. The resulting HDLC data and status information is passed to the partial packet buffer processor to be stored in the appropriate channel FIFO buffer. The configuration of the HDLC processor is accessed using indirect channel read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle generated by the upstream Receive Channel Assigner block (RCAS672). Writing new provisioning data to a channel resets the channel's entire state vector. 9.5.2 Partial Packet Buffer Processor The partial packet buffer processor controls the 32 Kbyte partial packet RAM which is divided into 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous sections of the RAM can be allocated in the partial packet buffer RAM to create a channel FIFO. System software is responsible for the assignment of blocks to individual channel FIFOs. Figure 3 shows an example of three blocks (blocks 1, 3, and 200) linked together to form a 48 byte channel FIFO.
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The partial packet buffer processor is divided into three sections: writer, reader and roamer. The writer is a time-sliced state machine which writes the HDLC data and status information from the HDLC processor into a channel FIFO in the packet buffer RAM. The reader transfers channel FIFO data from the packet buffer RAM to the downstream Receive DMA Controller block (RMAC672). The roamer is a time-sliced state machine which tracks channel FIFO buffer depths and signals the reader to service a particular channel. If a buffer over-run occurs, the writer ends the current packet from the HDLC processor in the channel FIFO with an over-run flag and ignores the rest of the packet. Figure 3 - Partial Packet Buffer Structure
Partial Packet Buffer RAM
Block 0 Block 1 Block 2 Block 3 16 bytes 16 bytes 16 bytes 16 bytes Block 0 Block 1 Block 2 Block 3
Block Pointer RAM
XX 0x03 XX 0xC8
Block 200
16 bytes
Block 200
0x01
Block 2047
16 bytes
Block 2047
XX
The FIFO algorithm of the partial packet buffer processor is based on a programmable per-channel transfer size. Instead of tracking the number of full blocks in a channel FIFO, the processor tracks the number of transactions. Whenever the partial packet writer fills a transfer-sized number of blocks or writes an end-of-packet flag to the channel FIFO, a transaction is created. Whenever the partial packet reader transmits a transfer-size number of blocks or an end-of-packet flag to the RMAC672 block, a transaction is deleted. Thus, small packets less than the transfer size will be naturally transferred to the
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RMAC672 block without having to precisely track the number of full blocks in the channel FIFO. The partial packet roamer performs the transaction accounting for all channel FIFOs. The roamer increments the transaction count when the writer signals a new transaction and sets a per-channel flag to indicate a non-zero transaction count. The roamer searches the flags in a round-robin fashion to decide for which channel FIFO to request transfer by the RMAC672 block. The roamer informs the partial packet reader of the channel to process. The reader transfers the data to the RMAC672 until the channel transfer size is reached or an end of packet is detected. The reader then informs the roamer that a transaction is consumed. The roamer updates its transaction count and clears the non-zero transaction count flag if required. The roamer then services the next channel with its transaction flag set high. The writer and reader determine empty and full FIFO conditions using flags. Each block in the partial packet buffer has an associated flag. The writer sets the flag after the block is written and the reader clears the flag after the block is read. The flags are initialized (cleared) when the block pointers are written using indirect block writes. The writer declares a channel FIFO overrun whenever the writer tries to store data to a block with a set flag. In order to support optional removal of the FCS from the packet data, the writer does not declare a block as filled (set the block flag nor increment the transaction count) until the first double word of the next block in channel FIFO is filled. If the end of a packet resides in the first double word, the writer declares both blocks as full at the same time. When the reader finishes processing a transaction, it examines the first double word of the next block for the end-of-packet flag. If the first double word of the next block contains only FCS bytes, the reader would, optionally, process next transaction (end-of-packet) and consume the block, as it contains information not transferred to the RMAC672 block.
9.6
Receive DMA Controller
The Receive DMA Controller block (RMAC672) is a DMA controller which stores received packet data in host computer memory. The RMAC672 is not directly connected to the host memory PCI bus. Memory accesses are serviced by a downstream PCI controller block (GPIC). The RMAC672 and the host exchange information using receive packet descriptors (RPDs). The descriptor contains the size and location of buffers in host memory and the packet status information associated with the data in each buffer. RPDs are transferred from the RMAC672 to the host and vice versa using descriptor reference queues. The RMAC672 maintains all the pointers for the operation of the queues. The RMAC672 provides two receive packet descriptor reference (RPDR) free queues to support small and large buffers. The RMAC672 acquires free buffers by reading RPDRs from the free queues. After a packet is received, the RMAC672
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places the associated RPDR onto a RPDR ready queue. To minimize host bus accesses, the RMAC672 maintains a descriptor reference table to store current DMA information. This table contains separate DMA information entries for up to 672 receive channels.
9.6.1 Data Structures
For packet data, the RMAC672 communicates with the host using Receive Packet Descriptors (RPD), Receive Packet Descriptor References (RPDR), the Receive Packet Descriptor Reference Ready (RPDRR) queue and the Receive Packet Descriptor Reference Small and Large Buffer Free (RPDRF) queues. The RMAC672 copies packet data to data buffers in host memory. The RPD, RPDR, RPDRR queue, and Small and Large RPDRF queues are data structures which are used to transfer host memory data buffer information. All five data structures are manipulated by both the RMAC672 and the host computer. The RPD holds the data buffer size, data buffer address, and packet status information. The RPDR is a pointer which is used to index into a table of RPDs. The RPDRR queue and RPDRF queues allow the RMAC672 and the host to pass RPDRs back and forth. These data structures are described in more detail in the following sections.
Receive Packet Descriptor
The Receive Packet Descriptors (RPDs) pass buffer and packet information between the RMAC672 and the host. Both the RMAC672 and the host read and write information in the RPDs. The host writes RPD fields which describe the size and address of data buffers in host memory. The RMAC672 writes RPD fields which provide number of bytes used in each data buffer, RPD link information, and the status of the received packet. RPDs are stored in host memory in a Receive Packet Descriptor Table which is described in a later section. The Receive Packet Descriptor structure is shown in Figure 4.
Figure 4 - Receive Packet Descriptor
Bit 31
Data Buf fer Start Address [31 :0] Bytes In Buffer [15:0] Reserved (6) RCC[9:0] Reserved (16) Status [5:0] Res (1) Offset[1:0] CE Reserved (7)
0
Next R PD Pointer [14:0] Receive Buff er Size [15 :0]
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Table 8 - Receive Packet Descriptor Fields Field Data Buffer Start Address[31:0] Description The Data Buffer Start Address[31:0] bits point to the data buffer in host memory. This field is expected to be configured by the Host during initialisation.
The Data Buffer Start Address field is valid in all RPDs. CE The Chain End (CE) bit indicates the end of a linked list of RPDs. When CE is set to logic one, the current RPD is the last RPD of a linked list of RPDs. When CE is set to logic zero, the current RPD is not the last RPD of a linked list. The CE bit is valid for all RPDs written by the RMAC672 to the Receive Ready Queue. When a packet requires only one RPD, the CE bit is set to logic one. The CE bit is ignored for all RPDs read by the RMAC672 from the Receive Free Queues, each of which is assumed to point to only one buffer, i.e. not a chain. Offset[1:0] The Offset[1:0] bits indicate the byte offset of the data packet from the start of the buffer. If this value is nonzero, there will be `dummy' (i.e. undefined) bytes at the start of the data buffer prior to the packet data proper. For a linked list of RPDs, only the first RPD's Offset field is valid. All other RPD Offset fields of the linked list are set to 0. Status [5:0] The Status[5:0] bits indicate the status of the received packet. Status[0] Status[1] Status[2] Status[3] Status[4] Status[5] Rx buffer overrun Packet exceeds max. allowed size CRC error Packet Length not an exact no. of bytes HDLC abort detected Unused (set to 0)
For a linked list of RPDs, only the last RPD's Status field is valid. All other RPD Status fields of the linked list are invalid and should be ignored. When a packet requires only one RPD, the Status field is valid.
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Field Bytes in Buffer [15:0]
Description The Bytes in Buffer[15:0] bits indicate the number of bytes actually used in the current RPD's data buffer to store packet data. The count excludes the 'dummy' bytes inserted as a result of a non-zero Offset field. A count greater than 32767 bytes indicates a packet that is shorter than the expected length of the FCS field.
The Bytes in Buffer field is invalid when Status[0] or Status[4] is asserted .
Next RPD Pointer [14:0]
The Next RPD Pointer[14:0] bits store a RPDR which enables the RMAC672 to support linked lists of RPDs. This field, which is only valid when CE is equal to logic zero, contains the RPDR to the next RPD in a linked list. The RMAC672 links RPDs when more than one buffer is needed to store a packet. The Next RPD Pointer is not valid for the last RPD in a linked list (when CE=1). When a packet requires only one RPD, the Next RPD Pointer field is not valid.
RCC[9:0]
The Receive Channel Code (RCC[9:0]) bits are used by the RMAC672 to associate a RPD with a channel. For a linked list of RPDs, all the RPDs' RCC[9:0] fields are valid. i.e. all contain the same channel value.
Receive Buffer Size The Receive Buffer Size[15:0] bits indicate the size in [15:0] bytes of the current RPD's data buffer. This field is expected to be configured by the Host during initialisation. The Receive Buffer Size must be a non-zero integer multiple of sixteen and less than or equal to 32752. The Receive Buffer Size field is valid in all RPDs. The Receive Buffer Size and Data Buffer Start Address fields are written only by the host. The RMAC672 reads these fields to determine where to store packet data. All other fields are written only by the RMAC672.
Receive Packet Descriptor Table
The Receive Packet Descriptor Table resides in host memory and stores all the RPDs. The RPD Table can contain a maximum of 32768 RPDs. The base of the RPD table is user programmable using the Rx Packet Descriptor Table Base (RPDTB) register. The table is indexed by a Receive Packet Descriptor Reference (RPDR) which is a 15-bit pointer defining the offset of a RPD from the
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table base. Thus, as shown in the following diagram, a RPD can be located by adding the RPDR to the Rx Packet Descriptor Table Base register.
Figure 5 - Receive Packet Descriptor Table
RPDTB[31:4] = Rx Packet Descriptor Table Base register RPDR[14:0] = Receive Packet Descriptor Reference RPD_ADDR[31:0] = Receive Packet Descriptor Address
Bit 31 RPDTB[31:4]
Bit 0
0000
+
RPDR[14:0]
0000
=
RPD_ADDR[31:0]
RPDTB RPD 1 RPD_ADDR RPD 2
Bit 31
Bit 0 Dword 0 Dword 1 Dword 2 Dword 3 Dword 0 Dword 3
Dword 0 RPD 32768 Dword 3
The Receive Packet Descriptor Table resides in host memory. The Rx Packet Descriptor Table Base register resides in the RMAC672; this register is initialised
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by the host. The RPDRs reside in host memory and are accessed using receive packet queues which are described in the next section.
Receive Packet Queues
Receive Packet Queues are used to transfer RPDRs between the host and the RMAC672. There are three queues: a RPDR Large Buffer Free Queue (RPDRLFQ), a RPDR Small Buffer Free Queue (RPDRSFQ) and a RPDR Ready Queue (RPDRRQ). The free queues contain RPDRs referencing RPDs that define free buffers. The ready queue contains RPDRs referencing RPDs that define buffers ready for host processing. The RMAC672 pulls RPDRs from the free queues when it needs free data buffers. The RMAC672 places an RPDR onto the ready queue after it has filled the buffers with data from each complete packet. The host removes RPDRs from the ready queue to process the data buffers. The host places the RPDRs back onto the free queues after it finishes reading the data from the buffers. When starting to process a packet, the RMAC672 uses a small buffer RPD to store the first buffer of packet data. If the packet data requires more than one buffer, the RMAC672 uses large buffer RPDs to store the remainder of the packet. The RMAC672 links together all the RPDs required to store the packet and returns the RPDR associated with the first RPD onto the ready queue. All receive packet queues reside in host memory and are defined by the Rx Queue Base (RQB) register and index registers which reside in the RMAC672. The Rx Queue Base is the base address for the receive packet queues. Each packet queue has four index registers which define the start and end of the queue and the read and write locations of the queue. Each index register is 16 bits in length and defines an offset from the Rx Queue Base. Thus, as shown in the Figure 6, the host address of a RPDR is calculated by adding the index register to the Rx Queue Base register. The host initializes the Rx Queue Base register and all the index registers. When an entity (either the RMAC672 or the host) removes elements from a queue, the entity updates the read pointer for that queue. When an entity (either the RMAC672 or the host) places elements onto a queue, the entity updates the write pointer for that queue. The read index for each queue points to the last valid RPDR read while the write index points to where the next RPDR can be written. The start index points to the first valid location within the queue; an RPDR can be written to this location. However, the end index points to a location that is beyond a queue; an RPDR can not be written to this location. Note however, the start index of one queue can be set to the end index of another queue. A queue is empty when the read index is one less than the write index; a queue is also empty if the read index is one less than the end index and the write index equals the start index. A queue is
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full when the read index is equal to the write index. Figure 6 shows the RPDR reference queues.
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Figure 6 - RPDRF and RPDRR Queues
Receive Packet Descriptor (RPD) Reference Queues Base Address:
RQB[3 1:2] = Rx Q ueue Base register
Index Registers:
Large Buffer Free Q ueue: RPDRLFQS[15:0] = RPDR L arge Free Queue Start register RPDRLFQW [15:0] = RPD R Large F ree Queue W rite regis ter RPDRLFQ R[15:0 ] = R PDR Large Free Queu e Read register RPDRLFQE [15:0] = RPD R Large F ree Qu eue End register Ready Q ueue: RPDRRQS[15:0] = RPDR R eady Q ueue Start register RPDRRQ W [15:0] = RPDR Ready Q ueue W rite register RPDRRQ R[15:0] = R PDR R eady Q ueue Read register RPDRRQ E[15:0 ] = RPDR Ready Queue End register Sm all Bu ffer Free Queue: RPDRSFQS[15:0] = RPDR Sm all F ree Queue Start register RPDRSFQW [15:0] = RPD R Sm all Free Queue W rite register RPDRSFQ R[15:0] = R PDR Sm all Free Queue Read register RPDRSFQE [15:0] = RPDR Sm all Free Queue End register
Base Address + Index Register ------------------------Host Address +
RQB[31:2] Index[1 5:0 ] AD[31:0]
00 00
Rx Packet Descriptor Reference Queue Mem ory Map
RPDRRQS RPDRRQR Bit 31 Status + R PDR Status + R PDR Status + R PDR Bit 0
Host Mem ory
RPDRRQW
Status + R PDR Status + R PDR Status + R PDR
RPDRRQE RQB RPDRLF QS RPDRLF QR RPDR RPDR RPDR RPD R eference Queues 256KB
RPDRLF QW
RPDR RPDR RPDR
RPDRLFQE RPDRSFQS RPDRSFQR
RPDR RPDR RPDR
Valid R PDR RPDRSFQW RPDR RPDR RPDRSFQE RPDR
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Note that the maximum value to which an end pointer may be set is FFFF hex, resulting in a maximum offset from the queue base address of (4*(FFFF-1)) = 3FFF8 hex. An end pointer must not be set to 0 hex in an attempt to include offset 3FFFC hex in a queue. As shown in Figure 6, the ready queue elements have a status field as well as an RPDR field. The RMAC672 fills in the status field to mark whether a packet was successfully received or not. The host reads the status field. The ready queue element is shown in Table 9 below along with the definition of the status bits. If the RMAC672 requires a buffer of a particular size (i.e. small or large) and no RPDR is available in the corresponding free queue, a RPDR from the other free queue is substituted. The host may, therefore, force the RMAC672 to store received data in buffers of only one size by setting one of the free queues to zero length, i.e. by setting the start and end index registers of one of the queues to equal values. If the RMAC672 requires a buffer and neither free queue contains RPDRs, an RPQ_ERRI interrupt is generated.
Table 9 - RPDRR Queue Element
Bit 16 STATUS[1:0] RPDR[14:0] Bit 0
Field
STATUS[1:0]
Description
The encoding for the status field is as follows: 00 - 01 - 10 - 11 - Successful reception of packet. Unsuccessful reception of packet. Unprovisioned partial packet. Partial packet returned due to RAWMAX limit being reached.
RPDR[14:0]
The RPDR[14:0] field defines the offset of the first RPD in a linked chain of RPDs, each pointing to a buffer containing the received data.
As described previously, the RMAC672 links RPDs together if more than one buffer is needed for a packet. The RMAC672 links additional buffer RPDs to the end of the chain as required until the entire packet is copied to host memory (provided that the host has not disabled use of both the small and large free queues by setting one of them to length zero). After storing the packet data, the RMAC672 places the STATUS+RPDR for the first RPD onto the ready queue. Only the RPDR associated with the first RPD is placed onto the ready queue. All other required RPDs are linked to the first RPD as shown in Figure 7.
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Although a STATUS+RPDR only totals to 17 bits, each queue entry is a dword, i.e. 32 bits. When the RMAC672 block writes a STATUS+RPDR to the ready queue, it sets the remaining 7 bits in the third byte to zero and the fourth byte is unmodified.
Figure 7 - RPDRR Queue Operation
Rx Packet Descriptor Reference Ready Queue
RP DRRQ _START _ADDR RPDR RQ _RE AD_ADDR RPD - 16 bytes
ST AT US + RPDR ST AT US + RPDR
Bit 31
Bit 0
buffer -packet M
RPDRRQ_W RITE_ADDR
ST AT US + RPDR
RPD - 16 bytes
buffer -packet N
RPD - 16 bytes
buffer -start of packet O
RPD - 16 bytes buffer -m iddle of packet O RPD - 16 bytes buffer -end of packet O
RP DRRQ _EN D_ADDR
Receive Channel Descriptor Reference Table
On a per-channel basis, the RMAC672 caches information such as the current DMA information in a Receive Channel Descriptor Reference (RCDR) Table. The RMAC672 can process 672 channels and stores three dwords of information per channel. This information is cached internally in order to
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decrease the number of host bus accesses required to process each data packet. The structure of the RCDR table is shown in Figure 8.
Figure 8 - Receive Channel Descriptor Reference Table
Bit 31 RCC 0 Bytes Avail. in Buffer[14:0] RBC[1:0] Buffer Size[14:0] RCC 1
R es
Bit 0 RPD Pointer[14:0] Start RPD Pointer[14:0] RPD Pointer[14:0] Start RPD Pointer[14:0]
V
DMA Current Address[31:0] Bytes Avail. in Buffer[14:0] RBC[1:0] Buffer Size[14:0]
R es
V
DMA Current Address[31:0]
RCC 671
Bytes Avail. in Buffer[14:0] RBC[1:0] Buffer Size[14:0]
R es
RPD Pointer[14:0] Start RPD Pointer[14:0]
V
DMA Current Address[31:0]
Table 10 - Receive Channel Descriptor Reference Table Fields Field
Bytes Available in Buffer[15:0]
Description
This field is used to keep track of the number of bytes available in the current data buffer. The RMAC672 initialises the Bytes Available in Buffer to the Receive Buffer Size minus the offset at the head of the buffer. The field is decremented each time a byte is written into the buffer. This field is used to keep track of the number of buffers used when storing `raw' (i.e. non packet delimited) data. The RMAC672 initialises the RBC field to the value of the RAWMAX[1:0] field in the RMAC Control Register. The field is decremented each time a buffer is filled with data. If the field reaches zero, the chain of RPDs is placed on the ready queue and a new chain started. This field contains the pointer to the current RPD.
RBC[1:0]
RPD Pointer[14:0]
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Field
Buffer Size[14:0] V
Description
This field contains the size in bytes of the buffer currently being written to. This bit (Valid) indicates whether a packet is currently being received on the DMA channel. When the V bit is set to 1, the other fields in the RCDR table entry for the DMA channel contain valid information. This field contains the pointer to the first RPD for the packet being received. The DMA Current Address [31:0] bits holds the host address of the next dword in the current buffer. The RMAC672 increments this field on each access to the buffer.
Start RPD Pointer[14:0] DMA Current Address[31:0]
9.6.2 DMA Transaction Controller
The DMA Transaction Controller coordinates the reception of data packets from the Receive Packet Interface and their subsequent storage in host memory. A packet may be received over a number of separate transactions, interleaved with transactions belonging to other DMA channels. As well as sending the received data to host memory, the DMA Transaction Controller initiates data transactions of its own for the purposes of maintaining the data structures (queues, descriptors, etc.) in host memory.
9.6.3 Write Data Pipeline/Mux
The Write Data Pipeline/Mux performs two functions. First, it pipelines receive data between the RHDL672 block and the GPIC block, inserting enough delay to enable the DMA Transaction Controller to generate appropriate control signals at the GPIC interface. Second, it provides a multiplexor to the data out lines on the GPIC interface, allowing the DMA Transaction Controller to output data relating to the transactions the controller itself initiates.
9.6.4 Descriptor Information Cache
The Descriptor Information Cache provides the storage for the Receive Channel Descriptor Reference (RCDR) Table described above (Figure 8).
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9.6.5 Free Queue Cache
The Free Queue Cache block implements the 6 element RPDR Small Buffer Free Queue cache and the 6 element RPDR Large Buffer Free Queue cache. These caches are used to store free small buffer and large buffer RPDRs. Caching RPDRs reduces the number of host bus accesses that the RMAC672 makes. Each cache is managed independently. The elements of the cache are consumed one at a time as they are needed by the RMAC672. The RPDR small buffer cache is reloaded when it is empty and the RMAC672 requires a new small buffer RPDR. The large buffer RPDR cache is reloaded when it is empty and the RMAC672 requires a new large buffer RPDR. When reloading either of the caches, the appropriate cache controller will read up to six new elements. The cache controller may read fewer than six elements if there are fewer than six new elements available, or the read pointer index is within six elements of the end of the free queue. If the read pointer is near the end of the free queue, the cache controller reads only to the end of the queue and does not start reading from the top of the queue until the next time a reload is required. To do so would require two host memory transactions and would be of no benefit.
9.7
PCI Controller
The General-Purpose Peripheral Component Interconnect Controller block (GPIC) provides a 32-bit Master and Target interface core which contains all the required control functions for full Peripheral Component Interconnect (PCI) Bus Revision 2.1 compliance. Communications between the PCI bus and other FREEDM-84P672 blocks can be made through either an internal asynchronous16-bit bus or through one of two synchronous FIFO interfaces. One of the FIFO interfaces is dedicated to servicing the Receive DMA Controller block (RMAC672) and the other to the Transmit DMA Controller block (TMAC672). The GPIC supports a 32-bit PCI bus operating at up to 66 MHz and bridges between the timing domain of the DMA controllers (SYSCLK) and the timing domain of the PCI bus (PCICLK). The GPIC is backwards compatible and will operate at 33 MHz when connected to a 33 MHz PCI bus. By itself, the GPIC does not generate any PCI bus accesses. All transactions on the bus are initiated by another PCI bus master or by the core device. The GPIC transforms each access to and from the PCI bus to the intended target or initiator in the core device. Except for the configuration space registers and parity generating/checking, the GPIC performs no operations on the data. The GPIC is made up of four sections: master state machine, a target state machine, internal microprocessor bus interface and error/bus controller. The
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target and master blocks operate independent of each other. The error/bus control block monitors the control signals from the target and master blocks to determine the state of the PCI I/O pads. This block also generates and/or checks parity for all data going to or coming from the PCI bus. The internal microprocessor bus interface block contains configuration and status registers together with the production test logic for the GPIC block.
9.7.1 Master Machine
The GPIC master machine translates requests from the RMAC672 and TMAC672 block interfaces into PCI bus transactions. The GPIC initiates four types of PCI cycles: memory read (burst or single), memory read multiple, memory read line and memory write (burst or single). The number of data transfers in any cycle is controlled by the DMA controllers. The maximum burst size is determined by the particular data path. A read cycle to the RMAC672 is restricted to a maximum burst size of 8 dwords and a write cycle is limited to a maximum of 64. The TMAC672 interface has a limit of 64 dwords on a read cycle and 8 on a write cycle. In response to a DMA controller requesting a cycle, the GPIC must arbitrate for control of the PCI bus. In the event that the RMAC672 and TMAC672 request service simultaneously, the GPIC66 processes the RMAC672 DMA operation first. When an external PCI bus arbitrator issues a Grant in response to the Request from the GPIC, the master state machine monitors the PCI bus to insure that the previous master has completed its transaction and has released the bus before beginning the cycle. Once the GPIC has control of the bus, it will assert the FRAME signal and drive the bus with the address and command. The value for the address is provided by the selected DMA controller. After the initial data transfer, the GPIC tracks the address for all remaining transfers in the burst internally in case the GPIC is disconnected by the target and must retry the transaction. The target of the GPIC master burst cycle has the option of stopping or disconnecting the burst at any point. In the event of a target disconnect the GPIC will terminate the present cycle and release the PCI bus. If the GPIC is asserting the REQUEST line at the time of the disconnect, it will remove the REQUEST for two PCI clock cycles then reassert it. When the PCI bus arbitrator returns the GRANT, the GPIC will restart the burst access at the next address and continue until the burst is completed or repeat the sequence if the target disconnects again. During burst reads, the GPIC accepts the data without inserting any wait states. Data is written directly into the read FIFO where the RMAC672 or TMAC672 can
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remove it at its own rate. During burst writes, the GPIC will output the data without inserting any wait states, but may terminate the transaction early if the local master fails to fill the write FIFO with data before the GPIC requires it. (If a write transaction is terminated early due to data starvation, the GPIC will automatically initiate a further transaction to write the remaining data when it becomes available.) Normally, the GPIC will begin requesting the PCI bus for a write transaction shortly after data starts to be loaded into the write FIFO by the RMAC672 or TMAC672. The RMAC672, however, is not required to supply a transaction length when writing packet data and in addition, may insert pauses during the transfer. In the case of packet data writes by the RMAC672, the GPIC will hold off requesting the PCI bus until the write FIFO has filled up with a number of dwords equal to a programmable threshold. If the FIFO empties without reaching the end of the transition, the GPIC will terminate the current transaction and restart a new transaction to transfer any remaining data when the RMAC672 signals an end of transaction. Beginning the PCI transaction before all the data is in the write FIFO allows the GPIC to reduce the impact of the bus latency on the core device. Each master PCI cycle generated by the GPIC can be terminated in three ways: Completion, Timeout or Master Abort. The normal mode of operation of the GPIC is to terminate after transferring all the data from the master FIFO selected. As noted above this may involve multiple PCI accesses because of the inability of the target to accept the full burst or data starvation during writes. After the completion of the burst transfer the GPIC will release the bus unless another FIFO is requesting service, in which case if the GRANT is asserted the GPIC will insert one idle cycle on the bus and then start a new transfer. The maximum duration of the a master burst cycle is controlled by the value set in the LATENCY TIMER register in the GPIC Configuration Register block. This value is set by the host on boot and is loaded into a counter in the GPIC master state at the start of each access. If the counter reaches zero and the GRANT signal has been removed the GPIC will release the bus regardless of whether it has completed the present burst cycle. This type of termination is referred to as a Master Time-out. In the case of a Master Time-out the GPIC will remove the REQUEST signal for two PCI clocks and then reassert it to complete the burst cycle. If no target responds to the address placed on the bus by the GPIC after 4 PCI clocks the GPIC will terminate the cycle and flag the cycle in the PCI Command/ Status Configuration Register as a Master Abort. If the Stop on Error enable (SOE_E) bit is set in the GPIC Command Register, the GPIC will not process any more requests until the error condition is cleared. If the SOE_E is not set, the GPIC will discard the REQUEST and indicate to the local master that the cycle is
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complete. This action will result in any write data being lost and any read data being erroneous.
9.7.2 Master Local Bus Interface
The master local bus is a 32 bit data bus which connects the local master device to the GPIC. The GPIC contains two local master interface blocks, with one supporting the RMAC672 and the other the TMAC672. Each local master interface has been optimised to support the traffic pattern generated by the RMAC672 or the TMAC672 and are not interchangeable. The data path between the GPIC and local master device provides a mechanism to segregate the system timing domain of the core from the PCI bus. Transfers on each of the RMAC672 and TMAC672 interfaces are timed to its own system clock. The DMA controllers isolated from all aspects of the PCI bus protocol, and instead "sees" a simple synchronous protocol. Read or write cycles on the local master bus will initiate a request for service to the GPIC which will then transfer the data via the PCI bus. The GPIC maximises data throughput between the PCI bus and the local device by paralleling local bus data transfers with PCI access latency. The GPIC allows either DMA controller to write data independent of each other and independent of PCI bus control. The GPIC temporarily buffers the data from each DMA controller while it is arbitrating for control of the PCI bus. After completion of a write transfer, the DMA controller is then released to perform other tasks. The GPIC can buffer only a single transaction from each DMA controller. Read accesses on the local bus are optimised by allowing the DMA controllers access to the data from the PCI bus as soon as the first data becomes available. After the initial synchronisation and PCI bus latency data is transferred at the slower of PCI bus rate or the core logic SYSCLK rate. Once a read transaction is started, the DMA controller is held waiting for the ready signal while the GPIC is arbitrating for the PCI bus. All data is passed between the GPIC and the DMA controllers in little Endian format and, in the default mode of operation, the GPIC expects all data on the PCI bus to also be in little Endian format. The GPIC provides a selection bit in the internal Control register which allows the Endian format of the PCI bus data to be changed. If enabled, the GPIC will swizzle all packet data on the PCI bus (but not descriptor references and the contents of descriptors). The swizzling is performed according to the "byte address invariance" rule, i.e. the only change to the data is the mirror-imaging of byte lanes. The interface for the RMAC672 provides for byte addressability of write transactions whereas the interface for the TMAC672 provides for byte
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addressability of read transactions. Other transactions must be dword aligned. For byte-addressable transactions, the data transferred between the local device and the GPIC need not be dword aligned with the data as it is presented on the PCI bus. The GPIC will perform any byte-realignment required. In order to complete a transfer involving byte re-alignment, the GPIC may need to add an extra burst cycle to the PCI transaction.
9.7.3 Target Machine
The GPIC target machine performs all the required functions of a stand alone PCI target device. The target block performs three main functions. The first is the target state machine which controls the protocol of PCI target accesses to the GPIC. The second function is to provide all PCI Configuration registers. Last, the target block provides a Target Interface to the CBI registers in the other FREEDM-84P672 blocks. The GPIC tracks the PCI bus and decodes all addresses and commands placed on the bus to determine whether to respond to the access. The GPIC responds to the following types of PCI bus commands only: Configuration read and write, memory read and write, memory-read-multiple and memory-read-line which are aliased to memory read and memory-write-and-invalidate which is aliased to memory write. The GPIC will ignore any access that falls within the address range but has any other command type. After accepting a target access as a medium speed device, the FREEDM84P672 inserts one wait state for a configuration read/write and five wait states for other command types before completing the transaction by asserting TRDYB. Burst accesses to the GPIC are accepted provided they are of linear type. If a master makes a memory access to the GPIC with the lower two address bits set to any value but "00" (linear burst type) the GPIC ignores the cycle. Burst accesses of any length are accepted, but the FREEDM-84P672 will disconnect if the master inserts any wait states during the transaction. The FREEDM-84P672 will also disconnect on every read and write access to configuration space after transferring one Dword of data. Figure 9 illustrates the GPIC address space.
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Figure 9 - GPIC Address Map
PCI ADDRESS MAP 0B
CBI Registers Base Address
CBI Registers
8KB
4GB
The GPIC responds with medium timing to master accesses. (i.e. DEVSELB is asserted 2 PCICLK cycles after FRAMEB asserted). The GPIC inserts five wait states on reads to the internal CBI register space (six wait states for the 2nd and subsequent dwords of a burst read). The target machine will only terminate an access with a Retry if the target is locked and another master tries to access the GPIC. The GPIC will terminate any access to a non-burst area with a Disconnect and always with data transferred. The target does not support delayed transactions. The GPIC will perform a Target-Abort termination only in the case of an address parity error in an address that the GPIC claims.
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9.7.4 CBI Bus Interface
The CBI bus interface provides access to the CBI address space of the FREEDM-84P672 blocks. The CBI address space is set by the associated BAR in the PCI Configuration registers. Write transfers to the CBI space always write all 32 bits provided that at least one byte enable is asserted. A write command with all byte enables negated will be ignored. Read transfers always return the 32 bits regardless of the status of the byte enables, as long as at least one byte enable is asserted. A read command with all byte enables negated will be ignored.
9.7.5 Error / Bus Control
The Error/Bus Control block monitors signals from both the Target block and Master Block to determine the direction of the PCI bus pads and to generate or check parity. After reset, the GPIC sets all bi-directional PCI bus pads to inputs and monitors the bus for accesses. The Error/Bus control unit remains in this state unless either the Master requests the PCI bus or the Target responds to a PCI Master Access. The Error/Bus control unit decodes the state of each state machine to determine the direction of each PCI bus signal. All PCI bus devices are required to check and generate even parity across AD[31:0] and C/BEB[3:0] signals. The GPIC generates parity on Master address and write data phases; the target generates parity on read data phases. The GPIC is required to check parity on all PCI bus phases even if it is not participating in the cycle. But, the GPIC will report parity errors only if the GPIC is involved in the PCI cycle or if the GPIC detects an address parity error or data parity is detected in a PCI special cycle. The GPIC updates the PCI Configuration Status register for all detected error conditions.
9.8
Transmit DMA Controller
The Transmit DMA Controller block (TMAC672) is a DMA controller which retrieves packet data from host computer memory for transmission. The minimum packet data length is two bytes. The TMAC672 communicates with the host computer bus through the master interface connected to PCI Controller block (GPIC) which translates host bus specific signals from the host to the master interface format. The TMAC672 uses the master interface whenever it wishes to initiate a host bus read or write; in this case, the TMAC672 is the initiator and the host memory is the target. The TMAC672 and the host exchange information using transmit descriptors (TDs). The descriptor contains the size and location of buffers in host memory
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and the packet status information associated with the data in each buffer. TDs are transferred from the TMAC672 to the host and vice versa using descriptor reference queues. The TMAC672 maintains all the pointers for the operation of the queues. The TMAC672 acquires buffers with data ready for transmission by reading TDRs from a TDR ready queue. After a packet has been transmitted, the TMAC672 places the associated TDR onto a TDR free queue. To minimise host bus accesses, the TMAC672 maintains a descriptor reference table to store current DMA information. This table contains separate DMA information entries for up to 672 transmit channels. The TMAC672 also performs per-channel sorting of packets received in the TDR ready queue to eliminate head-of-line blocking.
9.8.1 Data Structures
The TMAC672 communicates with the host using Transmit Descriptors (TD), Transmit Descriptor References (TDR), the Transmit Data Reference Ready (TDRR) queue and the Transmit Data Reference Free (TDRF) queue. The TMAC672 reads packet data from data buffers in host memory. The TD, TDR, TDRR queue, and TDRF queue are data structures which are used to transfer host memory data buffer information. All four data structures are manipulated by both the TMAC672 and the host computer. The TD holds the data buffer size, data buffer address, and other packet information. The TDR is a pointer which is used to index into a table of TDs. The TDRR queue and TDRF queue allow the TMAC672 and the host to pass TDRs back and forth. These data structures are described in more detail in the following sections.
Transmit Descriptor
The Transmit Descriptors (TDs) pass buffer and packet information between the TMAC672 and the host. Both the TMAC672 and the host read and write information in the TDs. TDs are stored in host memory in a Transmit Descriptor Table. The Transmit Descriptor structure is shown in Figure 10.
Figure 10 - Transmit Descriptor
Bit 31
Data Buf fer Start Address [31:0] Bytes In Buffer [15:0] V TM AC Next TD P ointer[14:0] Reserved (16) P AB T IOC CE Res (2) M TCC[9:0]
0
H ost Next TD P ointer[14 :0] Transm it Buf fer Size[15:0]
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Table 11 - Transmit Descriptor Fields Field
Data Buffer Start Address [31:0] Bytes In Buffer [15:0]
Description
The Data Buffer Start Address[31:0] bits point to the data buffer in host memory. The Data Buffer Start Address field is valid in all TDs The Bytes In Buffer[15:0] field is used by the host to indicate the total number of bytes to be transmitted in the current TD. Zero length buffers are illegal. The Priority bit is set by the host to indicate the priority of the associated packet in a two level quality of service scheme. Packets with its P bit set high are queued in the high priority queue in the TMAC672. Packets with the P bit set low are queued in the low priority queue. Packets in the low priority queue will not begin transmission until the high priority queue is empty. The Abort (ABT) bit is used by the host to abort the transmission of a packet. When ABT is set to logic 1, the packet will be aborted after all the data in the buffer has been transmitted. If ABT is set to logic 1 in the current TD, the M bit must be set low and the CE bit must be set to high. The Interrupt On Complete (IOC) bit is used by the host to instruct the TMAC672 to interrupt the host when the current TD's data buffer has been read. When IOC is logic 1, the TMAC672 asserts the IOCI interrupt when the data buffer has been read. Additionally, the Free Queue FIFO will be flushed. If IOC is logic zero, the TMAC672 will not generate an interrupt and the Free Queue FIFO will operate normally.
P
ABT
IOC
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Field
CE
Description
The Chain End (CE) bit is used by the host to indicate the end of a linked list of TDs presented to the TMAC672. The linked list can contain one or more packets as delineated by the M bit (see above). When CE is set to logic 1, the current TD is the last TD of a linked list of TDs. When CE is set to logic 0, the current TD is not the last TD of a linked list. When the current TD is not the last of the linked list, the Host Next TD Pointer[14:0] field is valid, otherwise the field is not valid. Note: When CE is set to logic 1, the only valid value for M is logic 0. Note: When presenting raw (i.e. unpacketised) data for transmission, the host should code the M and CE bits as for a single packet chain, i.e. M=1, CE=0 for all TDs except the last in the chain and M=0, CE=1 for the last TD in the chain.
TCC[9:0]
The Transmit Channel Code (TCC[9:0]) bits are used by the host to associate a channel with a TD pointed to by a TDR. All TCC[9:0] fields in a linked list of TDs must be set to the same value.
V
The V bit is used to indicate that the TMAC Next TD Pointer field is valid. When set to logic 1, the TMAC Next TD Pointer[14:0] field is valid. When V is set to logic 0, the TMAC Next TD Pointer[14:0] field is invalid. The V bit is used by the host to reclaim data buffers in the event that data presented to the TMAC672 is returned to the host due to a channel becoming unprovisioned. The V bit is expected to be initialised to logic 0 by the host.
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Field
TMAC Next TD Pointer [14:0]
Description
The TMAC Next TD Pointer[14:0] bits are used to store TDRs which permits the TMAC672 to create linked lists of TDs passed to it via the TDRR queue. The TDs are linked with other TDs belonging to the same channel and same priority level. In the case that data presented to the TMAC672 is returned to the host due to a channel becoming unprovisioned, a TDR pointing to the start of the per-channel linked list of TDs is placed on the TDRF queue. It is the responsibility of the host to follow the TMAC672 and host links in order to recover all the buffers. The More (M) bit is used by the host to support packets that require multiple TDs. If M is set to logic 1, the current TD is just one of several TDs for the current packet. If M is set to logic 0, this TD either describes the entire packet (in the single TD packet case) or describes the end of a packet (in the multiple TD packet case). Note: When M is set to logic 1, the only valid value for CE is logic 0.
M
Host Next TD Pointer [14:0]
The Host Next TD Pointer[14:0] bits are used to store TDRs which permits the host to support linked lists of TDs. As described above, linked lists of TDs are terminated by setting the CE bit to logic 1. Linked lists of TDs are used by the host to pass multiple TD packets or multiple packets associated with the same channel and priority level to the TMAC672. The Transmit Buffer Size[15:0] field is used to indicate the size in bytes of the current TD's data buffer. (N.B. The TMAC672 does not make use of this field.)
Transmit Buffer Size [15:0]
Transmit Descriptor Table
The Transmit Descriptor Table, which resides in host memory, contains all of the Transmit Descriptors referenced by the TMAC672. To access a TD, the TMAC672 takes a TDR from a TDRR queue or from the TCDR table and adds 16 times its value (because each TD is 16 bytes in size) to the Transmit Descriptor Table Base (TDTB) pointer to form the actual address of the TD in host memory. Each TD must reside in the Transmit Descriptor Table. The
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Transmit Descriptor Table can contain a maximum of 32768 TDs. The base of the Transmit Descriptor Table is user programmable using the TMAC Tx Descriptor Table Base register. Thus, as shown below, each TD can be located using a Transmit Descriptor Reference (TDR) combined with the TMAC Tx Descriptor Table Base register.
Figure 11 - Transmit Descriptor Table
TDTB[31:4] = Tx Descriptor Table Base register TDR[14:0] = Transmit Descriptor Reference TD_ADDR[31:0] = Transmit Descriptor Address
Bit 31 TDTB[31:4]
Bit 0
0000
+
TDR[14:0]
0000
=
TD_ADDR[31:0]
TDTB TD1 TD_ADDR TD2
Bit 31
Bit 0 Dword 0 Dword 1 Dword 2 Dword 3 Dword 0 Dword 3
Dword 0 TD 32768 Dword 3
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Transmit Queues
Pointers to the transmit descriptors (TDs) containing packet(s) ready for transmission are passed from the host to the TMAC672 using the Transmit Descriptor Reference Ready (TDRR) queue, which resides in host memory. Pointers to transmit descriptor structures whose buffers have been read by the TMAC672 are passed from the TMAC672 to the host using the Transmit Descriptor Reference Free (TDRF) queue, which also resides in host memory. The TMAC672 contains a Free Queue cache which can store up to six TDRs. If caching is enabled, free TDRs are written into the TDRF queue six at a time, to reduce the number of host memory accesses. The Free Queue cache is flushed to the TDRF queue if the Interrupt On Completion (IOC) bit is set in the TD, which sends the corresponding TDR directly to the TDRF queue. The Free Queue cache is also flushed to the TDRF queue if the FQFLUSH register bit is set high. The FQFLUSH register bit is self clearing. The queues, shown in Figure 12 are defined by a common base pointer residing in the Transmit Queue Base register and eight offset pointers, four per queue. For each queue, two pointers define the start and the end of the queue, and two pointers keep track of the current read and write locations within the queue. The read pointer for each queue points to the offset of the last valid TDR read, and the write pointer points to the offset where next TDR can be written. The end of a queue is not a valid location for a TDR to be read or written. A queue is empty when the read pointer is one less than the write pointer or if the read pointer is one less than the end pointer and the write pointer equals the start pointer. A queue is full when the read pointer is equal to the write pointer. Each queue element is 32 bits in size, but only the least significant 18 bits are valid. The 18 least significant bits consist of a 15-bit TDR and three status bits for the TD pointed at by this TDR. The status bits are used by the TMAC672 to inform the host of the success or failure of transmission (see Table 12). When the TMAC672 writes TDRs to the TDRF queue, it sets bits [23:18] of the queue element to 0 and leaves bits [31:24] unaltered. Once a TDR is placed on the TDRF queue, the FREEDM-84P672 will make no further accesses to the TD nor the associated buffer. Note that the maximum value to which an end pointer may be set is FFFF hex, resulting in a maximum offset from the queue base address of (4*(FFFF-1)) = 3FFF8 hex. An end pointer must not be set to 0 hex in an attempt to include offset 3FFFC hex in a queue.
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Figure 12 - TDRR and TDRF Queues
Transmit Descriptor Referance Queues Base Address:
TQB[31:2] = Tx Queue Base register
Index Registers:
Ready: TDRRQS[15:0] = TDRRQW[15:0] = TDRRQR[15:0] = TDRRQE[15:0] = Free: TDRFQS[15:0] = TDRFQW[15:0] = TDRFQR[15:0] = TDRFQE[15:0] = TDR Free Queue Start register TDR Free Queue Write register TDR Free Queue Read register TDR Free Queue End register TDR Ready Queue Start register TDR Ready Queue Write register TDR Ready Queue Read register TDR Ready Queue End register
Base Address + Index Register ------------------------PCI Address
TQB[31:2]
00
+
Index[15:0] 00 AD[31:0]
Tx Descriptor Reference Queue Memory Map
TDRFQS TDRFQR Bit 31 Status + TDR Status + TDR Status + TDR Bit 0
PCI Host Memory
Status + TDR TDRFQW Status + TDR Status + TDR TDRFQE TDRRQS TDRRQR TDR TDR TDR TQB TDR Reference Queues 256KB
TDRRQW TDRRQE
TDR TDR TDR Valid TDR
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Table 12 - Transmit Descriptor Reference
Bit 17 STATUS[2:0] TDR[14:0] Bit 0
Field
Status[2:0]
Description
The TMAC672 fills in the Status field to indicate to the host the results of processing the TD. The encoding is: Status[1:0] 00 01 10 11 Status[2] 0 1 Description Last or only buffer of packet, buffer read. Buffer of partial packet, buffer read. Unprovisioned channel, buffer not read. Malformed packet (e.g. Bytes In Buffer field set to 0), buffer not read. Description No underflow detected. Underflow detected.
TDR[14:0]
The TDR[14:0] field contains the offset of the TD returned.
If a TDR is returned to the host with the status field set to "10" (unprovisioned channel), the TDR may point to a binary tree of TDs and buffers (as indicated by the CE and V bits in the TDs). It is the responsibility of the host to traverse the tree to reclaim all the buffers. If a TDR is returned to the host with the status field set to any other value, the TDR will only point to one TD and buffer regardless of the values of V and CE in that TD. The underflow status bit (Status[2]) is normally attached to the TDR belonging to a packet experiencing underflow. For long packets spanning multiple buffers, underflow is reported only once at the first available TDR of that channel. All subsequent TDRs of that packet will be returned normally without the underflow status. In rare cases, due to internal buffering by the FREEDM-84P672, a packet may experience underflow at the very end of a packet, just as the TDR is being returned to the TDR free queue. The underflow status will then be reported in the first TDR of the immediate next packet of that channel. Because of the uncertainty with the reporting of underflows between the current verse the subsequent packet, the underflow status should only be used to gather performance statistics on channels and not for initiating packet specific responses such as retransmission.
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Transmit Channel Descriptor Reference Table
The TMAC672 maintains a Transmit Channel Descriptor Reference (TCDR) table in which is stored certain information relating to DMA activity on each channel together with TD pointers which are used by the TMAC672 to sort packet chains supplied by the host into per-channel linked lists (see below). The caching of DMA-related information reduces the number of host bus accesses required to process each data packet, while the sorting into per-channel linked lists eliminates head of line blocking. Each channel is provided with two entries in the TCDR table, one for high priority packets (Pri 1) and one for low priority packets (Pri 0). The structure of the TCDR table is shown in Figure 13 below.
Figure 13 - Transmit Channel Descriptor Reference Table
Bit 33 TCC 0, Pri 0
Res Res Res
Bit 0
Reserved (12)
NA
Abrt IOC
M CE A
D
Res
Current TD Pointer [14:0] Host TD Pointer [14:0] Next TD Pointer [14:0] Current TD Pointer [14:0] Host TD Pointer [14:0] Next TD Pointer [14:0]
Bytes to Tx [15:0]
PiP
DMA Current Address[31:0] Last TD Pointer [14:0]
NA
Abrt IOC
U
V D
Res
TCC 1, Pri 0
Res Res Res
Reserved (12)
M CE A
Bytes to Tx [15:0]
PiP
DMA Current Address[31:0] Last TD Pointer [14:0]
V
U
TCC 671, Pri 1
Res Res Res
Reserved (12)
NA
Abrt IOC
M CE A
D
Res
Current TD Pointer [14:0] Host TD Pointer [14:0] Next TD Pointer [14:0]
Bytes to Tx [15:0]
PiP
DMA Current Address[31:0] Last TD Pointer [14:0]
V
U
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Table 13 - Transmit Channel Descriptor Reference Table Fields Field
NA
Description
Indicates that a `null abort' is to be sent to the downstream block when it next requests data on this channel. The NA bit is set if a mal-formed TD is encountered while searching down a host chain. A copy of the ABRT bit in the TD currently being read. A copy of the IOC bit in the TD currently being read. A copy of the M bit in the TD currently being read. A copy of the CE bit in the TD currently being read. Indicates if this channel is active (i.e. provisioned). If the channel is active, the A bit is set to logic 1. If the channel is inactive, the A bit is set to logic 0. Indicates whether the linked list of packets for this channel is empty or not. If the D bit is set to logic 1, the list is not empty and the current TD pointer field is valid (i.e., it points to a valid TD). If the D bit is set to logic 0, the list is empty and the current TD pointer field is invalid. Offset to the TD currently being read. (See Figure 14) The Bytes to Tx[15:0] bits are used to indicate the total number of bytes that remain to be read in the current buffer. Each access to the data buffer decrements this value. A value of zero in this field indicates the buffer has been completely read.
ABRT IOC M CE A
D
Current TD Pointer [14:0] Bytes To Tx[15:0]
Host TD Pointer [14:0] A copy of the Host Next TD Pointer field of the TD currently being read, i.e. a pointer to the next TD in the chain currently being read. (See Figure 14) DMA Current Address[31:0] U The DMA Current Address [31:0] bits hold the address of the next dword in the current buffer. This field is incremented on each access to the buffer. Indicates that an underflow has occurred on this channel. This bit is set in response to an underflow indication for the downstream THDL672 block and is cleared when a TDR is written to the TDR Free Queue (or to the free queue cache).
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Field
PiP
Description
The Packet Transfer in Progress bit indicates that a packet is currently being transmitted on this channel at this priority level. Offset to the head of the last host-linked chain of TDs to be read. (See Figure 14) Indicates if the linked list of packets for this channel contains more than one host-linked chain (See Figure 14). If the V bit is set to logic 1, the list contains more than one chain and the next and last TD pointer fields are valid. If the V bit is set to logic 0, the list is either empty or contains only one host-linked chain and the next and last TD pointer fields are invalid.
Last TD Pointer [14:0] V
Next TD Pointer [14:0] Offset to the head of the next host-linked chain of TDs to be read. (See Figure 14)
Transmit Descriptor Linking
As described above, the TCDR table contains pointers which the TMAC672 uses to construct linked lists of data packets to be transmitted. After the host places a new TDR in the TDR Ready queue, the TMAC672 retrieves the TDR and links it to the TD pointed at by the Last TD Pointer field. The TMAC672 may create up to 1,344 linked lists, viz. a high-priority list and a low-priority list for each DMA channel. Whenever a new data packet is requested by the downstream block, the TMAC672 picks a packet from the high-priority linked list unless it is empty, in which case, a packet from the low-priority linked list is used.
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Figure 14 - TD Linking
TD Curr. Next Last Host TDR TDR TDR TDR P1
V=1 M=1 CE=0 TMAC Link
TD P3
V=1 M=1 CE=0 TMAC Link
TD P4
V=0 M=0 CE=1
TCDR Table
Host Link
Data
Host Link
Data
TD P1
M=1 CE=0
TD P3
M=0 CE=1
Data
Host Link
Data
TD P1
M=0 CE=0
Data
Host Link
TD P2
M=0 CE=1
Data
The host links the TDs vertically while the TMAC672 links TDs horizontally. Figure 14 shows the TDs for packets P1 and P2 linked by the host before the TDR is placed on the TDRR queue, as are the TDs for packet P3 and P4. Packet P3 is linked to packet P1 by the TMAC672, as is packet P4 linked to
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packet P3. The TMAC672 indicates valid horizontal links by setting the V bit to logic 1.
9.8.2 Task Priorities
The TMAC672 must perform a number of tasks concurrently in order to maintain a steady flow of data through the system. The main tasks of the TMAC672 are managing the Ready Queue (i.e. removing chains of data packets from the queue and attaching them to the appropriate per-channel linked list) and servicing requests for data from the Transmit Packet Interface. The priority of service for each of the tasks is fixed by the TMAC672 as follows: * * * Top priority is given to servicing `expedited' read requests from the Transmit HDLC Processor / Partial Packet Buffer block (THDL672). Second priority is given to removing chains of data packets from the TDRR queue and attaching them to the appropriate per-channel linked list. Third priority is given to servicing non-expedited read requests from the THDL672.
9.8.3 DMA Transaction Controller
The DMA Transaction Controller coordinates the processing of requests from the THDL672 with the reading of data stored in host memory. The reading of a data packet may require a number of separate host memory transactions, interleaved with transactions of other DMA channels. As well as reading data from the Host Master Interface, the DMA Transaction Controller initiates read and write transactions to the PCI Controller block (GPIC) for the purposes of maintaining the data structures (queues, descriptors, etc.) in host memory.
9.8.4 Read Data Pipeline
The Read Data Pipeline inserts delay in the data stream between the GPIC interface and the THDL672 interface to enable the DMA Transaction Controller to generate appropriate control signals at the Transmit Packet Interface.
9.8.5 Descriptor Information Cache
The Descriptor Information Cache provides the storage for the Transmit Channel Descriptor Reference (TCDR) Table.
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9.8.6 Free Queue Cache
The Free Queue Cache block implements the 6 element TDR Free Queue cache. Caching TDRs reduces the number of host bus accesses that the TMAC672 makes. TDRs are written to the cache one at a time as they are released by the TMAC672. The cache is then flushed to host memory when it becomes full, when a TD with the IOC bit set high is released, when the FQFLUSH register bit is set high or when a TD is released as the result of unprovisioning a channel. The cache controller may also flush the cache when it contains fewer than six elements or if the pointer index is within six elements of the end of the free queue. When the write pointer is near the end of the free queue, the cache controller writes only to the end of the queue and does not start writing from the top of the queue until the next time a flush is required. To do so would require two host memory transactions and would be of no benefit.
9.9
Transmit HDLC Controller / Partial Packet Buffer
The Transmit HDLC Controller / Partial Packet Buffer block (THDL672) contains a partial packet buffer for PCI latency control and a transmit HDLC controller. Packet data retrieved from the PCI host memory by the Transmit DMA Controller block (TMAC672) is stored in channel specific FIFOs residing in the partial packet buffer. When the amount of data in a FIFO reaches a programmable threshold, the HDLC controller is enabled to initiate transmission. The HDLC controller performs flag generation, bit stuffing and, optionally, frame check sequence (FCS) insertion. The FCS is software selectable to be CRC-CCITT or CRC-32. The minimum packet size, excluding FCS, is two bytes. A single byte payload is illegal. The HDLC controller delivers data to the Transmit Channel Assigner block (TCAS672) on demand. A packet in progress is aborted if an under-run occurs. The THDL672 is programmable to operate in transparent mode where packet data retrieved from the PCI host is transmitted verbatim.
9.9.1 Transmit HDLC Processor
The HDLC processor is a time-slice state machine which can process up to 672 independent channels. The state vector and provisioning information for each channel is stored in a RAM. Whenever the TCAS672 requests data, the appropriate state vector is read from the RAM, processed and finally written back to the RAM. The HDLC state-machine can be configured to perform flag insertion, bit stuffing and CRC generation. The HDLC processor requests data from the partial packet processor whenever a request for channel data arrives. However, the HDLC processor does not start transmitting a packet until the entire packet is stored in the channel FIFO or until the FIFO free space is less than the
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software programmable limit. If a channel FIFO under-runs, the HDLC processor aborts the packet. The configuration of the HDLC processor is accessed using indirect channel read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle inserted by the TCAS672 block. Writing new provisioning data to a channel resets the channels entire state vector.
9.9.2 Transmit Partial Packet Buffer Processor
The partial packet buffer processor controls the 32 Kbyte partial packet RAM which is divided into 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous sections of RAM can be allocated in the partial packet buffer RAM to create a channel FIFO. Figure 15 shows an example of three blocks (blocks 1, 3, and 200) linked together to form a 48 byte channel FIFO. The three pointer values would be written sequentially using indirect block write accesses. When a channel is provisioned with this FIFO, the state machine can be initialised to point to any one of the three blocks. The partial packet buffer processor is divided into three sections: reader, writer and roamer. The roamer is a time-sliced state machine which tracks each channel's FIFO buffer free space and signals the writer to service a particular channel. The writer requests data from the TMAC672 block and transfers packet data from the TMAC672 to the associated channel FIFO. The reader is a timesliced state machine which transfers the HDLC information from a channel FIFO to the HDLC processor when the HDLC processor requests it. If a buffer underrun occurs for a channel, the reader informs the HDLC processor and purges the rest of the packet.
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Figure 15 - Partial Packet Buffer Structure Partial Packet Buffer RAM
Block 0 Block 1 Block 2 Block 3 16 bytes 16 bytes 16 bytes 16 bytes Block 0 Block 1 Block 2 Block 3
Block Pointer RAM
XX 0x03 XX 0xC8
Block 200
16 bytes
Block 200
0x01
Block 2047
16 bytes
Block 2047
XX
The writer and reader determine empty and full FIFO conditions using flags. Each block in the partial packet buffer has an associated flag. The writer sets the flag after the block is written and the reader clears the flag after the block is read. The flags are initialized (cleared) when the block pointers are written using indirect block writes. The reader declares a channel FIFO under-run whenever it tries to read data from a block without a set flag. The FIFO algorithm of the partial packet buffer processor is based on perchannel software programmable transfer size and free space trigger level. Instead of tracking the number of full blocks in a channel FIFO, the processor tracks the number of empty blocks, called free space, as well as the number of end of packets stored in the FIFO. Recording the number of empty blocks instead of the number of full blocks reduces the amount of information the roamer must store in its state RAM. The partial packet roamer records the FIFO free space and end-of-packet count for all channel FIFOs. When the reader signals that a block has been read, the roamer increments the FIFO free space and sets a per-channel request flag if
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the free space is greater than the limit set by XFER[3:0]. The roamer also decrements the end-of-packet count when the reader signals that it has passed an end of a packet to the HDLC processor. If the HDLC is transmitting a packet and the FIFO free space is greater than the free space trigger level and there are no complete packets within the FIFO (end-of-packet count equal to zero), a perchannel starving flag is set. The roamer searches the starving flags in a roundrobin fashion to decide which channel FIFO should make expedited data requests to the TMAC672 block. If no starving flags are set, the roamer searches the request flags in a round-robin fashion to decide which channel FIFO should make regular data requests to the TMAC672 block. The roamer informs the partial packet writer of the channel FIFO to process, the FIFO free space and the type of request it should make. The writer sends a request for data to the TMAC672 block and writes the response data to the channel FIFO setting block full flags. The writer reports back to the roamer the number of blocks and end-of-packets transferred. The maximum amount of data transferred during one request is limited by a software programmable limit. The configuration of the HDLC processor is accessed using indirect channel read and write operations as well as indirect block read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle identified by the TCAS672 block. Writing new provisioning data to a channel resets the entire state vector.
9.10 Transmit Channel Assigner
The Transmit Channel Assigner block (TCAS672) processes up to 672 channels. Data for all channels is sourced from a single byte-serial stream from the Transmit HDLC Controller / Partial Packet Buffer block (THDL672). The TCAS672 demultiplexes the data and assigns each byte to any one of 84 links. When sending data to the SBI SIPO blocks, each link may be configured to support channelised T1/J1/E1 traffic, unchannelised DS-3 traffic or unframed traffic at T1/J1, E1 or DS-3 rates. When sending data to the TD outputs, links 0, 1 and 2 support unchannelised data at arbitary rates up to 51.84 Mbps. Each link is independent and has its own associated clock. The 84 TCAS links have a fixed relationship to the SPE and tributary numbers on the SBI ADD BUS as shown in the following table.
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Table 14 - SBI SPE/Tributary to TCAS Link Mapping SBI SPE No. 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
SBI Trib. No. 1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
TCAS Link No. 0
3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 75 78
SBI SPE No. 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
SBI Trib. No. 1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
TCAS Link No. 1
4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67 70 73 76 79
SBI SPE No. 3
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
SBI Trib. No. 1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
77
TCAS Link No. 2
5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80
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SBI SPE No. 1
SBI Trib. No. 28
TCAS Link No. 81
SBI SPE No. 2
SBI Trib. No. 28
TCAS Link No. 82
SBI SPE No. 3
SBI Trib. No. 28
TCAS Link No. 83
As shown in the table above, TCAS links 0, 1, and 2 are mapped to tributary 1 of SPEs 1, 2 and 3 respectively. These links may be configured to operate at DS-3 rate. (They may also be configured to output data to the TD outputs at rates up to 51.84 Mbps.) For each of these high-speed links, the TCAS672 provides a six byte FIFO. For the remaining links (TCAS links 3 to 83, mapped to links 2 to 28 of each SPE), the TCAS672 provides a single byte holding register. The TCAS672 performs parallel to serial conversion to form bit-serial streams which are passed to the SBI SIPO blocks. In the event where multiple links are in need of data, TCAS672 requests data from upstream blocks on a fixed priority basis with link 0 having the highest priority and link 83 the lowest. Links containing a T1/J1 or an E1 stream may be channelised. Data at each time-slot may be independently assigned to be sourced from a different channel. The position of T1/J1 and E1 framing bits/bytes is identified by frame pulse signals generated by the SBI SIPO blocks. With knowledge of the transmit link and time-slot identity, the TCAS672 performs a table look-up to identify the channel from which a data byte is to be sourced. Links containing a DS-3 stream are unchannelised, in which case, all data bytes on the link belong to one channel. The TCAS672 performs a table look-up to identify the channel to which a data byte belongs using only the outgoing link identity, as no time-slots are associated with unchannelised links. Links may additionally be configured to operate in an unframed "clear channel" mode, in which case the FREEDM-84P672 will output HDLC data in all bit positions, including those normally reserved for framing information. Links so configured operate as unchannelised regardless of link rate and the TCAS672 performs a table lookup using only the link number to determine the associated channel.
9.10.1 Line Interface
There are 84 line interface blocks in the TCAS672. Each line interface block contains a bit counter, an 8-bit shift register and a holding register that, together, perform parallel to serial conversion. Whenever the shift register is updated, a request for service is sent to the priority encoder block. When acknowledged by the priority encoder, the line interface responds by writing the data into the holding register. To support channelised links, each line interface block contains a time-slot counter. The time-slot counter is incremented each time the shift register is
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updated and is reset on detection of a frame pulse from the SBI SIPO blocks. For unchannelised or unframed links, the time-slot counter is held reset.
9.10.2 Priority Encoder
The priority encoder monitors the line interfaces for requests and synchronises them to the SYSCLK timing domain. Requests are serviced on a fixed priority scheme where highest to lowest priority is assigned from the line interface attached to link 0 to that attached to link 83. Thus, simultaneous requests from link `m' will be serviced ahead of link `n', if m < n. The priority encoder selects the request from the link with the highest priority for service. When there are no pending requests, the priority encoder generates an idle cycle. In addition, once every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests are serviced. This cycle is used by the channel assigner upstream for CBI accesses to the channel provision RAM.
9.10.3 Channel Assigner
The channel assigner block determines the channel number of the request currently being processed. The block contains a 2688 word channel provision RAM. The address of the RAM is constructed from concatenating the link number and the time-slot number of the highest priority requester. The fields of each RAM word include the channel number and a time-slot enable flag. The time-slot enable flag labels the current time-slot as belonging to the channel indicted by the channel number field. For time-slots that are enabled, the channel assigner issues a request to the THDL672 block which responds with packet data within one byte period of the transmit stream.
9.11 SBI Inserter and SIPO
The SBI transmit circuitry consists of an SBI Insert block and three SBI Serial to Parallel Converter (SBI SIPO) blocks. Each SIPO block processes data for one of the three Synchronous Payload Envelopes (SPEs) conveyed on the SBI ADD BUS. It receives serial data on either 28 links running at T1/J1 rate, 21 links at E1 rate or a single link at DS-3 rate and converts it to an internal parallel bus format. The SBI Insert block receives data from the SIPO blocks in the internal format and transmits it on the SBI ADD BUS. The SIPO blocks generate the serial clocks for the TCAS672 and thus are able to control the rate at which data is transmitted on to the SBI. The SBI Insert block can command the SIPO blocks to speed up or slow down these clocks in response to justfication requests received on the SBI interface. The SBI Insert block also contains FIFO circuitry to compensate for short term variations in the
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rate at which data is output by the TCAS672 and the rate at which it is transmitted on the SBI ADD BUS. The SBI Insert block may be configured to enable or disable transmission of individual triburaries on to the SBI ADD bus. Individual triburaries may also be configured to operate in framed or unframed mode.
9.12 Performance Monitor
The Performance Monitor block (PMON) contains four counters. The first two accumulate receive partial packet buffer FIFO overrun events and transmit partial packet buffer FIFO underflow events, respectively. The remaining two counters are software programmable to accumulate a variety of events, such as receive packet count, FCS error counts, etc. All counters saturate upon reaching maximum value. The accumulation logic consists of a counter and holding register pair. The counter is incremented when the associated event is detected. Writing to the FREEDM-84P672 Master Clock / Frame Pulse Activity Monitor and Accumulation Trigger register transfer the count to the corresponding holding register and clear the counter. The contents of the holding register is accessible via the PCI interface.
9.13 JTAG Test Access Port Interface
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The FREEDM-84P672 identification code is 073840CD hexadecimal.
9.14 PCI Host Interface
The FREEDM-84P672 supports two different normal mode register types as defined below: 1. PCI Host Accessible registers (PA) - these registers can be accessed through the PCI Host interface. 2. PCI Configuration registers (PC) - these register can only be accessed through the PCI Host interface during a PCI configuration cycle. The PCI registers are addressable on dword boundaries only. The PCI offset shown in the table below must be combined with a base address to form the PCI Interface address. The base address can be found in the FREEDM-84P672 Memory Base Address register in the PCI Configuration memory space.
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Table 15 - Normal Mode PCI Host Accessible Register Memory Map PCI Offset
0x000 0x004 0x008 0x00C 0x010 0x014 0x018 - 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 - 0x07C 0x080 0x084 - 0x0FC 0x100 0x104 0x108 0x10C 0x110 - 0x13C 0x140
Register
FREEDM-84P672 Master Reset FREEDM-84P672 Master Interrupt Enable FREEDM-84P672 Master Interrupt Status FREEDM-84P672 Master Clock / Frame Pulse Activity Monitor and Accumulation Trigger Reserved FREEDM-84P672 Master Line Loopback Reserved FREEDM-84P672 Master Performance Monitor Control FREEDM-84P672 Master SBI Interrupt Enable FREEDM-84P672 Master SBI Interrupt Status FREEDM-84P672 Master Tributary Loopback #1 FREEDM-84P672 Master Tributary Loopback #2 FREEDM-84P672 Master Tributary Loopback #3 FREEDM-84P672 Master Tributary Loopback #4 FREEDM-84P672 Master Tributary Loopback #5 FREEDM-84P672 Master Tributary Loopback #6 FREEDM-84P672 SBI DROP BUS Master Configuration FREEDM-84P672 SBI ADD BUS Master Configuration Reserved GPIC Control GPIC Reserved RCAS Indirect Channel and Time-slot Select RCAS Indirect Channel Data RCAS Reserved RCAS Channel Disable RCAS Reserved RCAS SBI SPE1 Configuration Register #1
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PCI Offset
0x144 0x148 0x14C 0x150 0x154 0x158 - 0x17C 0x180 - 0x188 0x18C - 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 - 0x21C 0x220 0x224 0x228 - 0x23C 0x240 - 0x27C 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C
Register
RCAS SBI SPE1 Configuration Register #2 RCAS SBI SPE2 Configuration Register #1 RCAS SBI SPE2 Configuration Register #2 RCAS SBI SPE3 Configuration Register #1 RCAS SBI SPE3 Configuration Register #2 RCAS Reserved RCAS Link #0 to #2 Configuration RCAS Reserved RHDL Indirect Channel Select RHDL Indirect Channel Data Register #1 RHDL Indirect Channel Data Register #2 RHDL Reserved RHDL Indirect Block Select RHDL Indirect Block Data Register RHDL Reserved RHDL Configuration RHDL Maximum Packet Length RHDL Reserved Reserved RMAC Control RMAC Indirect Channel Provisioning RMAC Packet Descriptor Table Base LSW RMAC Packet Descriptor Table Base MSW RMAC Queue Base LSW RMAC Queue Base MSW RMAC Packet Descriptor Reference Large Buffer Free Queue Start RMAC Packet Descriptor Reference Large Buffer Free Queue Write
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PCI Offset
0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC 0x2C0 0x2C4 0x2C8 - 0x2FC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334
Register
RMAC Packet Descriptor Reference Large Buffer Free Queue Read RMAC Packet Descriptor Reference Large Buffer Free Queue End RMAC Packet Descriptor Reference Small Buffer Free Queue Start RMAC Packet Descriptor Reference Small Buffer Free Queue Write RMAC Packet Descriptor Reference Small Buffer Free Queue Read RMAC Packet Descriptor Reference Small Buffer Free Queue End RMAC Packet Descriptor Reference Ready Queue Start RMAC Packet Descriptor Reference Ready Queue Write RMAC Packet Descriptor Reference Ready Queue Read RMAC Packet Descriptor Reference Ready Queue End RMAC Reserved TMAC Control TMAC Indirect Channel Provisioning TMAC Descriptor Table Base LSW TMAC Descriptor Table Base MSW TMAC Queue Base LSW TMAC Queue Base MSW TMAC Descriptor Reference Free Queue Start TMAC Descriptor Reference Free Queue Write TMAC Descriptor Reference Free Queue Read TMAC Descriptor Reference Free Queue End TMAC Descriptor Reference Ready Queue Start TMAC Descriptor Reference Ready Queue Write TMAC Descriptor Reference Ready Queue Read TMAC Descriptor Reference Ready Queue End
83
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PCI Offset
0x338 - 0x37C 0x380 0x384 0x388 0x38C 0x390 - 0x39C 0x3A0 0x3A4 0x3A8 - 0x3AC 0x3B0 0x3B4 - 0x3BC 0x3C0 - 0x3FC 0x400 0x404 0x408 0x40C 0x410 0x414 - 0x43C 0x440 0x444 0x448 0x44C 0x450 0x454 0x458 - 0x47C 0x480 - 0x488 0x48C - 0x4FC 0x500 0x504
Register
TMAC Reserved THDL Indirect Channel Select THDL Indirect Channel Data #1 THDL Indirect Channel Data #2 THDL Indirect Channel Data #3 THDL Reserved THDL Indirect Block Select THDL Indirect Block Data THDL Reserved THDL Configuration THDL Reserved Reserved TCAS Indirect Channel and Time-slot Select TCAS Indirect Channel Data TCAS Reserved TCAS Idle Time-slot Fill Data TCAS Channel Disable TCAS Reserved TCAS SBI SPE1 Configuration Register #1 TCAS SBI SPE1 Configuration Register #2 TCAS SBI SPE2 Configuration Register #1 TCAS SBI SPE2 Configuration Register #2 TCAS SBI SPE3 Configuration Register #1 TCAS SBI SPE3 Configuration Register #2 TCAS Reserved TCAS Link #0 to #2 Configuration TCAS Reserved PMON Status PMON Receive FIFO Overflow Count
84
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PCI Offset
0x508 0x50C 0x510 0x514 - 0x51C 0x520 - 0x5BC 0x5C0 0x5C4 - 0x5C8 0x5CC 0x5D0 0x5D4 0x5D8 0x5DC 0x5E0 - 0x5FC 0x600 - 0x67C 0x680 0x684 - 0x688 0x68C 0x690 0x694 0x698 0x69C - 0x6FC 0x700 - 0x7FC
Register
PMON Transmit FIFO Underflow Count PMON Configurable Count #1 PMON Configurable Count #2 PMON Reserved Reserved SBI EXTRACT Control SBI EXTRACT Reserved SBI EXTRACT Tributary RAM Indirect Access Address SBI EXTRACT Tributary RAM Indirect Access Control SBI EXTRACT Reserved SBI EXTRACT Tributary RAM Indirect Access Data SBI EXTRACT Parity Error Interrupt Reason SBI EXTRACT Reserved Reserved SBI INSERT Control SBI INSERT Reserved SBI INSERT Tributary RAM Indirect Access Address SBI INSERT Tributary RAM Indirect Access Control SBI INSERT Reserved SBI INSERT Tributary RAM Indirect Access Data SBI INSERT Reserved Reserved
The following PCI configuration registers are implemented by the PCI Interface. These registers can only be accessed when the PCI Interface is a target and a configuration cycle is in progress as indicated using the IDSEL input.
Table 16 - PCI Configuration Register Memory Map PCI Offset
0x00
Register
Vendor Identification/Device Identification
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PCI Offset
0x04 0x08 0x0C 0x10 0x14 - 0x24 0x28 - 0x38 0x3C
Register
Command/Status Revision Identifier/Class Code Cache Line Size/Latency Timer/Header Type/BIST CBI Memory Base Address Register Unused Base Address Register Reserved Interrupt Line/Interrupt Pin/MIN_GNT/MAX_LAT
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10
NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the FREEDM-84P672.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. Except where noted, all configuration bits that can be written into can also be read back. This allows the processor controlling the FREEDM-84P672 to determine the programming state of the block. 3. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect FREEDM-84P672 operation unless otherwise noted. 5. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the FREEDM84P672 operates as intended, reserved register bits must only be written with their default values. Similarly, writing to reserved registers should be avoided.
10.1 PCI Host Accessible Registers
PCI host accessible registers can be accessed by the PCI host. For each register description below, the hexadecimal register number indicates the PCI offset from the base address in the FREEDM-84P672 CBI Register Base Address Register when accesses are made using the PCI Host Port.
Note
These registers are not byte addressable. Writing to any one of these registers modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to the register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x000 : FREEDM-84P672 Master Reset Bit
Bit 31 to Bit 16 Bit 15 Bit 14 to Bit 0 R/W
Type
Function
Unused
Default
XXXXH
Reset Unused
0 XXXXH
This register provides software reset capability.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. RESET: The RESET bit allows the FREEDM-84P672 to be reset under software control. If the RESET bit is a logic one, the entire FREEDM-84P672 except the PCI Interface is held in reset. This bit is not self-clearing. Therefore, a logic zero must be written to bring the FREEDM-84P672 out of reset. Holding the FREEDM-84P672 in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset.
Note
Unlike the hardware reset input (RSTB), RESET does not force the FREEDM84P672's PCI pins tristate. RESET causes all registers to be set to their default values.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x004 : FREEDM-84P672 Master Interrupt Enable Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TFUDRE IOCE TDFQEE TDQRDYE TDQFE RPDRQEE RPDFQEE RPQRDYE RPQLFE RPQSFE RFOVRE RPFEE RABRTE RFCSEE PERRE SERRE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides interrupt enables for various events detected or initiated by the FREEDM-84P672.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SERRE: The system error interrupt enable bit (SERRE) enables PCI system error interrupts to the PCI host. When SERRE is set high, any address parity error, data parity error on Special Cycle commands, reception of a master abort or detection of a target abort will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when SERRE is set low. However, the SERRI bit remains valid when interrupts are disabled and may be polled to detect PCI system error events. PERRE: The parity error interrupt enable bit (PERRE) enables PCI parity error interrupts to the PCI host. When PERRE is set high, data parity errors detected by the FREEDM-84P672 or parity errors reported by a target will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when PERRE is set low. However, the PERRI bit remains valid when interrupts are disabled and may be polled to detect PCI parity error events. RFCSEE: The receive frame check sequence error interrupt enable bit (RFCSEE) enables receive FCS error interrupts to the PCI host. When RFCSEE is set high, a mismatch between the received FCS code and the computed CRC residue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RFCSEE is set low. However, the RFCSEI bit remains valid when interrupts are disabled and may be polled to detect receive FCS error events. RABRTE: The receive abort interrupt enable bit (RABRTE) enables receive HDLC abort interrupts to the PCI host. When RABRTE is set high, receipt of an abort code (at least 7 contiguous 1's) will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RABRTE is set low. However, the RABRTI bit remains valid when interrupts are disabled and may be polled to detect receive abort events. RPFEE: The receive packet format error interrupt enable bit (RPFEE) enables receive packet format error interrupts to the PCI host. When RPFEE is set high, receipt of a packet that is longer than the maximum specified in the RHDL Maximum Packet Length register, of a packet that is shorter than 32 bits (CRC-CCITT) or 48 bits (CRC-32), or of a packet that is not octet aligned will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPFEE is set low. However, the RPFEI bit remains valid when
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
interrupts are disabled and may be polled to detect receive packet format error events. RFOVRE: The receive FIFO overrun error interrupt enable bit (RFOVRE) enables receive FIFO overrun error interrupts to the PCI host. When RFOVRE is set high, attempts to write data into the logical FIFO of a channel when it is already full will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RFOVRE is set low. However, the RFOVRI bit remains valid when interrupts are disabled and may be polled to detect receive FIFO overrun events. RPQSFE: The receive packet descriptor small buffer free queue cache read interrupt enable bit (RPQSFE) enables receive packet descriptor small free queue cache read interrupts to the PCI host. When RPQSFE is set high, reading a programmable number of RPDR blocks from the RPDR Small Buffer Free Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPQSFE is set low. However, the RPQSFI bit remains valid when interrupts are disabled and may be polled to detect RPDR small buffer free queue cache read events. RPQLFE: The receive packet descriptor large buffer free queue cache read interrupt enable bit (RPQLFE) enables receive packet descriptor large free queue cache read interrupts to the PCI host. When RPQLFE is set high, reading a programmable number of RPDR blocks from the RPDR Large Buffer Free Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPQLFE is set low. However, the RPQLFI bit remains valid when interrupts are disabled and may be polled to detect RPDR large buffer free queue cache read events. RPQRDYE: The receive packet descriptor ready queue write interrupt enable bit (RPQRDYE) enables receive packet descriptor ready queue write interrupts to the PCI host. When RPQRDYE is set high, writing a programmable number of RPDRs to the RPDR Ready Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPQRDYE is set low. However, the RPQRDYI bit remains valid when interrupts are disabled and may be polled to detect RPDR ready queue write events.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RPDFQEE: The receive packet descriptor free queue error interrupt enable bit (RPDFQEE) enables receive packet descriptor free queue error interrupts to the PCI host. When RPDFQEE is set high, attempts to retrieve an RPDR when both the large buffer and small buffer free queues are empty will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPDFQEE is set low. However, the RPDFQEI bit remains valid when interrupts are disabled and may be polled to detect RPDR free queue empty error events. RPDRQEE: The receive packet descriptor ready queue error interrupt enable bit (RPDRQEE) enables receive packet descriptor ready queue error interrupts to the PCI host. When RPDRQEE is set high, attempts to write an RPDR when ready queue is ready full will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPDRQEE is set low. However, the RPDRQEI bit remains valid when interrupts are disabled and may be polled to detect RPDR ready queue full error events. TDQFE: The transmit packet descriptor free queue write interrupt enable bit (TDQFE) enables transmit packet descriptor free queue write interrupts to the PCI host. When TDQFE is set high, writing a programmable number of TDRs to the TDR Free Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when TDQFE is set low. However, the TDQFI bit remains valid when interrupts are disabled and may be polled to detect TDR free queue write events. TDQRDYE: The transmit descriptor ready queue cache read interrupt enable bit (TDQRDYE) enables transmit descriptor ready queue cache read interrupts to the PCI host. When TDQRDYE is set high, reading a programmable number of TDRs from the TDR Ready Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when TDQRDYE is set low. However, the TDQRDYI bit remains valid when interrupts are disabled and may be polled to detect TDR ready queue cache read events. TDFQEE: The transmit descriptor free queue error interrupt enable bit (TDFQEE) enables transmit descriptor free queue error interrupts to the PCI host. When TDFQEE is set high, attempting to write to the transmit free queue while the queue is full will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when TDFQEE is set low. However, the TDFQEI bit
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remains valid when interrupts are disabled and may be polled to detect TD free queue error events. IOCE: The transmit interrupt on complete enable bit (IOCE) enables transmission complete interrupts to the PCI host. When IOCE is set high, complete transmission of a packet with the IOC bit in the TD set high will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when IOCE is set low. However, the IOCI bit remains valid when interrupts are disabled and may be polled to detect transmission of IOC tagged packets. TFUDRE: The transmit FIFO underflow error interrupt enable bit (TFUDRE) enables transmit FIFO underflow error interrupts to the PCI host. When TFUDRE is set high, attempts to read data from the logical FIFO when it is already empty will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when TFUDRE is set low. However, the TFUDRI bit remains valid when interrupts are disabled and may be polled to detect transmit FIFO underflow events.
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93
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x008 : FREEDM-84P672 Master Interrupt Status Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R R R R R R R R R R
Type
Function
Unused
Default
XXXXH
TFUDRI IOCI TDFQEI TDQRDYI TDQFI RPDRQEI RPDFQEI RPQRDYI RPQLFI RPQSFI RFOVRI RPFEI RABRTI RFCSEI PERRI SERRI
X X X X X X X X X X X X X X X X
This register reports the interrupt status for various events detected or initiated by the FREEDM-84P672. Reading this registers acknowledges and clears the interrupts.
Note
This register is not byte addressable. Reading this register clears all the interrupt bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SERRI: The system error interrupt status bit (SERRI) reports PCI system error interrupts to the PCI host. SERRI is set high upon detection of any address parity error, data parity error on Special Cycle commands, reception of a master abort or detection of a target abort event. The SERRI bit remains valid when interrupts are disabled and may be polled to detect PCI system error events. PERRI: The parity error interrupt status bit (PERRI) reports PCI parity error interrupts to the PCI host. PERRI is set high when data parity errors are detected by the FREEDM-84P672 while acting as a master, and when parity errors are reported to the FREEDM-84P672 by a target via the PERRB input. The PERRI bit remains valid when interrupts are disabled and may be polled to detect PCI parity error events. RFCSEI: The receive frame check sequence error interrupt status bit (RFCSEI) reports receive FCS error interrupts to the PCI host. RFCSEI is set high, when a mismatch between the received FCS code and the computed CRC residue is detected. RFCSEI remains valid when interrupts are disabled and may be polled to detect receive FCS error events. RABRTI: The receive abort interrupt status bit (RABRTI) reports receive HDLC abort interrupts to the PCI host. RABRTI is set high upon receipt of an abort code (at least 7 contiguous 1's). RABRTI remains valid when interrupts are disabled and may be polled to detect receive abort events. RPFEI: The receive packet format error interrupt status bit (RPFEI) reports receive packet format error interrupts to the PCI host. RPFEI is set high upon receipt of a packet that is longer than the maximum programmed length, of a packet that is shorter than 32 bits (CRC-CCITT) or 48 bits (CRC-32), or of a packet that is not octet aligned. RPFEI remains valid when interrupts are disabled and may be polled to detect receive packet format error events. RFOVRI: The receive FIFO overrun error interrupt status bit (RFOVRI) reports receive FIFO overrun error interrupts to the PCI host. RFOVRI is set high on attempts to write data into the logical FIFO of a channel when it is already full. RFOVRI remains valid when interrupts are disabled and may be polled to detect receive FIFO overrun events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 95
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RPQSFI: The receive packet descriptor small buffer free queue cache read interrupt status bit (RPQSFI) reports receive packet descriptor small free queue cache read interrupts to the PCI host. RPQSFI is set high when the programmable number of RPDR blocks is read from the RPDR Small Buffer Free Queue. RPQSFI remains valid when interrupts are disabled and may be polled to detect RPDR small buffer free queue cache read events. RPQLFI: The receive packet descriptor large buffer free queue cache read interrupt status bit (RPQLFI) reports receive packet descriptor large free queue cache read interrupts to the PCI host. RPQLFI is set high when the programmable number of RPDR blocks is read from the RPDR Large Buffer Free Queue. RPQLFI remains valid when interrupts are disabled and may be polled to detect RPDR large buffer free queue cache read events. RPQRDYI: The receive packet descriptor ready queue write interrupt status bit (RPQRDYI) reports receive packet descriptor ready queue write interrupts to the PCI host. RPQRDYI is set high when the programmable number of RPDRs is written to the RPDR Ready Queue. RPQRDYI remains valid when interrupts are disabled and may be polled to detect RPDR ready queue write events. RPDFQEI: The receive packet descriptor free queue error interrupt status bit (RPDFQEI) reports receive packet descriptor free queue error interrupts to the PCI host. RPDFQEI is set high upon attempts to retrieve an RPDR when both the large buffer and small buffer free queues are empty. RPDFQEI remains valid when interrupts are disabled and may be polled to detect RPDR free queue empty error events. RPDRQEI: The receive packet descriptor ready queue error interrupt status bit (RPDRQEI) reports receive packet descriptor ready queue error interrupts to the PCI host. RPDRQEI is set high upon attempts to write an RPDR when ready queue is ready full. RPDRQEI remains valid when interrupts are disabled and may be polled to detect RPDR ready queue full error events. TDQFI: The transmit packet descriptor free queue write interrupt status bit (TDQFI) reports transmit packet descriptor free queue write interrupts to the PCI host. TDQFI is set high when the programmable number of TDRs is written to the
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TDR Free Queue. TDQFI remains valid when interrupts are disabled and may be polled to detect TDR free queue write events. TDQRDYI: The transmit descriptor ready queue cache read interrupt status bit (TDQRDYI) reports transmit descriptor ready queue cache read interrupts to the PCI host. TDQRDYI is set high when the programmable number of TDRs is read from the TDR Ready Queue. TDQRDYI remains valid when interrupts are disabled and may be polled to detect TDR ready queue cache read events. TDFQEI: The transmit descriptor free queue error interrupt status bit (TDFQEI) reports transmit descriptor free queue error interrupts to the PCI host. TDFQEI is set high when an attempt to write to the transmit free queue fail due to the queue being already full. TDFQEI bit remains valid when interrupts are disabled and may be polled to detect TD free queue error events. IOCI: The transmit interrupt on complete status bit (IOCI) reports transmission complete interrupts to the PCI host. IOCI is set high, when a packet with the IOC bit in the TD set high is completely transmitted. IOCI remains valid when interrupts are disabled and may be polled to detect transmission of IOC tagged packets. TFUDRI: The transmit FIFO underflow error interrupt status bit (TFUDRI) reports transmit FIFO underflow error interrupts to the PCI host. TFUDRI is set high upon attempts to read data from the logical FIFO when it is already empty. TFUDRI remains valid when interrupts are disabled and may be polled to detect transmit FIFO underflow events.
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97
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x00C : FREEDM-84P672 Master Clock / Frame Pulse Activity Monitor and Accumulation Trigger Bit
Bit 31 to Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R
Type
Function
Unused
Default
XXXXXXXH
C1FPA FASTCLKA REFCLKA SYSCLKA
X X X X
This register provides activity monitoring on the FREEDM-84P672 clock and SBI frame pulse inputs. When a monitored input makes a transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point, all the bits in this register are cleared. A lack of transitions is indicated by the corresponding register bit reading low. This register should be read periodically to detect for stuck at conditions. Writing to this register delimits the accumulation intervals in the PMON accumulation registers. Counts accumulated in those registers are transferred to holding registers where they can be read. The counters themselves are then cleared to begin accumulating events for a new accumulation interval. The bits in this register are not affected by write accesses.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. SYSCLKA: The system clock active bit (SYSCLKA) monitors for low to high transitions on the SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is set low when this register is read.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
REFCLKA: The SBI reference clock active bit (REFCLKA) monitors for low to high transitions on the REFCLK input. REFCLKA is set high on a rising edge of REFCLK, and is set low when this register is read. FASTCLKA: The SBI fast clock active bit (FASTCLKA) monitors for low to high transitions on the FASTCLK input. FASTCLKA is set high on a rising edge of FASTCLK, and is set low when this register is read. C1FPA: The SBI frame pulse active bit (C1FPA) monitors for low to high transitions on the C1FP input. C1FPA is set high on a rising edge of C1FP, and is set low when this register is read.
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99
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x014 : FREEDM-84P672 Master Line Loopback Bit
Bit 31 to Bit 16 Bit 15 to Bit 3 Bit 2 Bit 1 Bit 0 R/W
Type
Function
Unused
Default
XXXXH
Reserved
0000H
R/W R/W R/W
LLBEN[2] LLBEN[1] LLBEN[0]
0 0 0
This register controls line loopback for the three serial data links (enabled when SPEn_EN is low).
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. LLBEN[2:0]: The line loopback enable bits (LLBEN[2:0]) control line loopback for links #2 to #0. When LLBEN[n] is set high, the data on RD[n] is passed verbatim to TD[n] which is then updated on the falling edge of RCLK[n]. TCLK[n] is ignored. When LLBEN[n] is set low, TD[n] is processed normally.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
100
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x024 : FREEDM-84P672 Master Performance Monitor Control Bit
Bit 31 to Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXH
TP2EN TABRT2EN RP2EN RLENE2EN RABRT2EN RFCSE2EN RSPE2EN Unused TP1EN TABRT1EN RP1EN RLENE1EN RABRT1EN RFCSE1EN RSPE1EN
0 0 0 0 0 0 0 X 0 0 0 0 0 0 0
This register configures the events that are accumulated in the two configurable performance monitor counters in the PMON block.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. RSPE1EN: The receive small packet error accumulate enable bit (RSPE1EN) enables counting of minimum packet size violation events. When RSPE1EN is set
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
high, receipt of a packet that is shorter than 32 bits (CRC-CCITT, Unspecified CRC or no CRC) or 48 bits (CRC-32) will cause the PMON Configurable Accumulator #1 register to increment. Small packet errors are ignored when RSPE1EN is set low. RFCSE1EN: The receive frame check sequence error accumulate enable bit (RFCSE1EN) enables counting of receive FCS error events. When RFCSE1EN is set high, a mismatch between the received FCS code and the computed CRC residue will cause the PMON Configurable Accumulator #1 register to increment. Receive frame check sequence errors are ignored when RFCSE1EN is set low. RABRT1EN: The receive abort accumulate enable bit (RABRT1EN) enables counting of receive HDLC abort events. When RABRT1EN is set high, receipt of an abort code (at least 7 contiguous 1's) will cause the PMON Configurable Accumulator #1 register to increment. Receive aborts are ignored when RABRT1EN is set low. RLENE1EN: The receive packet length error accumulate enable bit (RLENE1EN) enables counting of receive packet length error events. When RLENE1EN is set high, receipt of a packet that is longer than the programmable maximum or of a packet that in not octet aligned will cause the PMON Configurable Accumulator #1 register to increment. (Receipt of a packet that is both too long and not octet aligned results in only one increment.) Receive packet length errors are ignored when RLENE1EN is set low. RP1EN: The receive packet enable bit (RP1EN) enables counting of receive error-free packets. When RP1EN is set high, receipt of an error-free packet will cause the PMON Configurable Accumulator #1 register to increment. Receive errorfree packets are ignored when RP1EN is set low. TABRT1EN: The transmit abort accumulate enable bit (TABRT1EN) enables counting of transmit HDLC abort events. When TABRT1EN is set high, insertion of an abort in the outgoing stream will cause the PMON Configurable Accumulator #1 register to increment. Transmit aborts are ignored when TABRT1EN is set low.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TP1EN: The transmit packet enable bit (TP1EN) enables counting of transmit error-free packets. When TP1EN is set high, transmission of an error-free packet will cause the PMON Configurable Accumulator #1 register to increment. Transmit error-free packets are ignored when TP1EN is set low. RSPE2EN: The receive small packet error accumulate enable bit (RSPE2EN) enables counting of minimum packet size violation events. When RSPE2EN is set high, receipt of a packet that is shorter than 32 bits (CRC-CCITT, Unspecified CRC or no CRC) or 48 bits (CRC-32) will cause the PMON Configurable Accumulator #2 register to increment. Small packet errors are ignored when RSPE2EN is set low. RFCSE2EN: The receive frame check sequence error accumulate enable bit (RFCSE2EN) enables counting of receive FCS error events. When RFCSE2EN is set high, a mismatch between the received FCS code and the computed CRC residue will cause the PMON Configurable Accumulator #2 register to increment. Receive frame check sequence errors are ignored when RFCSE2EN is set low. RABRT2EN: The receive abort accumulate enable bit (RABRT2EN) enables counting of receive HDLC abort events. When RABRT2EN is set high, receipt of an abort code (at least 7 contiguous 2's) will cause the PMON Configurable Accumulator #2 register to increment. Receive aborts are ignored when RABRT2EN is set low. RLENE2EN: The receive packet length error accumulate enable bit (RLENE2EN) enables counting of receive packet length error events. When RLENE2EN is set high, receipt of a packet that is longer than the programmable maximum or of a packet that in not octet aligned will cause the PMON Configurable Accumulator #2 register to increment. (Receipt of a packet that is both too long and not octet aligned results in only one increment.) Receive packet length errors are ignored when RLENE2EN is set low. RP2EN: The receive packet enable bit (RP2EN) enables counting of receive error-free packets. When RP2EN is set high, receipt of an error-free packet will cause the PMON Configurable Accumulator #2 register to increment. Receive errorfree packets are ignored when RP2EN is set low.
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TABRT2EN: The transmit abort accumulate enable bit (TABRT2EN) enables counting of transmit HDLC abort events. When TABRT2EN is set high, insertion of an abort in the outgoing stream will cause the PMON Configurable Accumulator #2 register to increment. Transmit aborts are ignored when TABRT2EN is set low. TP2EN: The transmit packet enable bit (TP2EN) enables counting of transmit error-free packets. When TP2EN is set high, transmission of an error-free packet will cause the PMON Configurable Accumulator #2 register to increment. Transmit error-free packets are ignored when TP2EN is set low.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x028 : FREEDM-84P672 Master SBI Interrupt Enable Bit
Bit 31 to Bit 1 Bit 0 R/W
Type
Function
Unused
Default
XXXXXXXXH
SBIEXTE
0
This register provides interrupt enables for various events detected or initiated by the SBI circuitry within the FREEDM-84P672.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. SBIEXTE: The SBI Extracter interrupt enable bit (SBIEXTE) enables interrupts from the SBI Extract block to the PCI host. When SBIEXTE is set high, an interrupt from the SBI Extract block will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when SBIEXTE is set low. However, the SBIEXTI bit remains valid when interrupts are disabled and may be polled to detect interrupts from the SBI Extract Block.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x02C : FREEDM-84P672 Master SBI Interrupt Status Bit
Bit 31 to Bit 1 Bit 0 R
Type
Function
Unused
Default
XXXXXXXXH
SBIEXTI
X
This register reports the interrupt status for various events detected or initiated by the SBI circuitry within the FREEDM-84P672. Reading this register acknowledges and clears the interrupts.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. SBIEXTI: The SBI Extracter interrupt status bit (SBIEXTI) reports an error condition from the SBI Extract block to the PCI host. SBIEXTI remains valid when interrupts are disabled and may be polled to detect SBI Extract block error conditions.
Note
The only error condition which the SBI Extract block reports is a parity error on the SBI DROP BUS. If parity errors occur, the SBI EXTRACT Parity Error Interrupt Reason register (0x5DC) may be read to obtain more detailed information concerning the error.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x030 : FREEDM-84P672 Master Tributary Loopback #1 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
SPE1_LBEN[16] SPE1_LBEN[15] SPE1_LBEN[14] SPE1_LBEN[13] SPE1_LBEN[12] SPE1_LBEN[11] SPE1_LBEN[10] SPE1_LBEN[9] SPE1_LBEN[8] SPE1_LBEN[7] SPE1_LBEN[6] SPE1_LBEN[5] SPE1_LBEN[4] SPE1_LBEN[3] SPE1_LBEN[2] SPE1_LBEN[1]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register controls line loopback for tributaries #1 to #16 of SPE #1.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. SPE1_LBEN[16:1]: The SPE #1 loopback enable bits (SPE1_LBEN[16:1]) control line loopback for tributaries #16 to #1 of SPE #1 of the SBI Interface. When
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SPE1_LBEN[n] is set high, the data on tributary #n output by the SBI PISO block is looped back to the tributary #n input of the SBI SIPO block. When SPE1_LBEN[n] is set low, transmit data for tributary #n is provided by the TCAS block (i.e. processed normally).
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x034 : FREEDM-84P672 Master Tributary Loopback #2 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
SPE2_LBEN[4] SPE2_LBEN[3] SPE2_LBEN[2] SPE2_LBEN[1] SPE1_LBEN[28] SPE1_LBEN[27] SPE1_LBEN[26] SPE1_LBEN[25] SPE1_LBEN[24] SPE1_LBEN[23] SPE1_LBEN[22] SPE1_LBEN[21] SPE1_LBEN[20] SPE1_LBEN[19] SPE1_LBEN[18] SPE1_LBEN[17]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register controls line loopback for tributaries #17 to #28 of SPE #1 and tributaries #1 to #4 of SPE #2.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SPE1_LBEN[28:17]: The SPE #1 loopback enable bits (SPE1_LBEN[28:17]) control line loopback for tributaries #28 to #17 of SPE #1 of the SBI Interface. When SPE1_LBEN[n] is set high, the data on tributary #n output by the SBI PISO block is looped back to the tributary #n input of the SBI SIPO block. When SPE1_LBEN[n] is set low, transmit data for tributary #n is provided by the TCAS block (i.e. processed normally). SPE2_LBEN[4:1]: The SPE #2 loopback enable bits (SPE2_LBEN[4:1]) control line loopback for tributaries #4 to #1 of SPE #2 of the SBI Interface. When SPE2_LBEN[n] is set high, the data on tributary #n output by the SBI PISO block is looped back to the tributary #n input of the SBI SIPO block. When SPE2_LBEN[n] is set low, transmit data for tributary #n is provided by the TCAS block (i.e. processed normally).
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x038 : FREEDM-84P672 Master Tributary Loopback #3 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
SPE2_LBEN[20] SPE2_LBEN[19] SPE2_LBEN[18] SPE2_LBEN[17] SPE2_LBEN[16] SPE2_LBEN[15] SPE2_LBEN[14] SPE2_LBEN[13] SPE2_LBEN[12] SPE2_LBEN[11] SPE2_LBEN[10] SPE2_LBEN[9] SPE2_LBEN[8] SPE2_LBEN[7] SPE2_LBEN[6] SPE2_LBEN[5]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register controls line loopback for tributaries #5 to #20 of SPE #2.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. SPE2_LBEN[20:5]: The SPE #2 loopback enable bits (SPE2_LBEN[20:5]) control line loopback for tributaries #20 to #5 of SPE #2 of the SBI Interface. When
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SPE2_LBEN[n] is set high, the data on tributary #n output by the SBI PISO block is looped back to the tributary #n input of the SBI SIPO block. When SPE2_LBEN[n] is set low, transmit data for tributary #n is provided by the TCAS block (i.e. processed normally).
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x03C : FREEDM-84P672 Master Tributary Loopback #4 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
SPE3_LBEN[8] SPE3_LBEN[7] SPE3_LBEN[6] SPE3_LBEN[5] SPE3_LBEN[4] SPE3_LBEN[3] SPE3_LBEN[2] SPE3_LBEN[1] SPE2_LBEN[28] SPE2_LBEN[27] SPE2_LBEN[26] SPE2_LBEN[25] SPE2_LBEN[24] SPE2_LBEN[23] SPE2_LBEN[22] SPE2_LBEN[21]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register controls line loopback for tributaries #21 to #28 of SPE #2 and tributaries #1 to #8 of SPE #3.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SPE3_LBEN[28:21]: The SPE #2 loopback enable bits (SPE2_LBEN[28:21]) control line loopback for tributaries #28 to #21 of SPE #2 of the SBI Interface. When SPE2_LBEN[n] is set high, the data on tributary #n output by the SBI PISO block is looped back to the tributary #n input of the SBI SIPO block. When SPE2_LBEN[n] is set low, transmit data for tributary #n is provided by the TCAS block (i.e. processed normally). SPE3_LBEN[8:1]: The SPE #3 loopback enable bits (SPE3_LBEN[8:1]) control line loopback for tributaries #8 to #1 of SPE #3 of the SBI Interface. When SPE3_LBEN[n] is set high, the data on tributary #n output by the SBI PISO block is looped back to the tributary #n input of the SBI SIPO block. When SPE3_LBEN[n] is set low, transmit data for tributary #n is provided by the TCAS block (i.e. processed normally).
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x040 : FREEDM-84P672 Master Tributary Loopback #5 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
SPE3_LBEN[24] SPE3_LBEN[23] SPE3_LBEN[22] SPE3_LBEN[21] SPE3_LBEN[20] SPE3_LBEN[19] SPE3_LBEN[18] SPE3_LBEN[17] SPE3_LBEN[16] SPE3_LBEN[15] SPE3_LBEN[14] SPE3_LBEN[13] SPE3_LBEN[12] SPE3_LBEN[11] SPE3_LBEN[10] SPE3_LBEN[9]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register controls line loopback for tributaries #9 to #24 of SPE #3.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. SPE3_LBEN[24:9]: The SPE #3 loopback enable bits (SPE3_LBEN[24:9]) control line loopback for tributaries #24 to #9 of SPE #3 of the SBI Interface. When
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SPE3_LBEN[n] is set high, the data on tributary #n output by the SBI PISO block is looped back to the tributary #n input of the SBI SIPO block. When SPE3_LBEN[n] is set low, transmit data for tributary #n is provided by the TCAS block (i.e. processed normally).
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x044 : FREEDM-84P672 Master Tributary Loopback #6 Bit
Bit 31 to Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXXH
SPE3_LBEN[28] SPE3_LBEN[27] SPE3_LBEN[26] SPE3_LBEN[25]
0 0 0 0
This register controls line loopback for tributaries #25 to #28 of SPE #3.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. SPE3_LBEN[28:25]: The SPE #3 loopback enable bits (SPE3_LBEN[28:25]) control line loopback for tributaries #28 to #25 of SPE #3 of the SBI Interface. When SPE3_LBEN[n] is set high, the data on tributary #n output by the SBI PISO block is looped back to the tributary #n input of the SBI SIPO block. When SPE3_LBEN[n] is set low, transmit data for tributary #n is provided by the TCAS block (i.e. processed normally).
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x048 : FREEDM-84P672 SBI DROP BUS Master Configuration Bit
Bit 31 to Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXH
Reserved Reserved FCLK_FREQ[1] FCLK_FREQ[0] SPE3_TYP[1] SPE3_TYP[0] SPE2_TYP[1] SPE2_TYP[0] SPE1_TYP[1] SPE1_TYP[0]
0 0 0 0 0 0 0 0 0 0
This register controls configures the operation of the SBI DROP BUS.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. SPEn_TYP[1:0]: The SPE type bits (SPEn_TYP[1:0]) determine the configuration of each of the three Synchronous Payload Envelopes conveyed on the SBI DROP BUS, according to the following table.
Table 17 - SPE Type Configuration SPEn_TYP[1:0] 00 01 10 11 Link Configuration 28 T1/J1 links 21 E1 links Single DS-3 link Reserved
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
FCLK_FREQ[1:0]: The FASTCLK frequency selector bits (FCLK_FREQ[1:0]) must be set according to the following table, depending on the frequency chosen for the FASTCLK input.
Table 18 - FASTCLK Frequency Selection FCLK_FREQ[1:0] 00 01 10 11
Reserved: The reserved bits must be set low for correct operation of the FREEDM84P672 device.
FASTCLK Frequency 51.84 MHz 44.928 MHz Reserved 66 MHz
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x04C : FREEDM-84P672 SBI ADD BUS Master Configuration Bit
Bit 31 to Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXH
PERM_DRV Reserved Reserved Reserved Reserved Reserved FCLK_FREQ[1] FCLK_FREQ[0] SPE3_TYP[1] SPE3_TYP[0] SPE2_TYP[1] SPE2_TYP[0] SPE1_TYP[1] SPE1_TYP[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register controls configures the operation of the SBI ADD BUS.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. SPEn_TYP[1:0]: The SPE type bits (SPEn_TYP[1:0]) determine the configuration of each of the three Synchronous Payload Envelopes conveyed on the SBI ADD BUS, according to the following table.
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Table 19 - SPE Type Configuration SPEn_TYP[1:0] 00 01 10 11
FCLK_FREQ[1:0]: The FASTCLK frequency selector bits (FCLK_FREQ[1:0]) must be set according to the following table, depending on the frequency chosen for the FASTCLK input.
Link Configuration 28 T1/J1 links 21 E1 links Single DS-3 link Reserved
Table 20 - FASTCLK Frequency Selection FCLK_FREQ[1:0] 00 01 10 11
Reserved: The reserved bits must be set low for correct operation of the FREEDM84P672 device. PERM_DRV: The Permanent Bus Driver selector bit (PERM_DRV) enables the FREEDM84P672 device to drive the SBI ADD BUS continously. When set to 1, the FREEDM-84P672 will drive the bus and assert the AACTIVE output at all times, provided that the ADETECT[1:0] inputs are both 0. When set to 0, the FREEDM-84P672 will only drive the bus and assert AACTIVE when it has data to send (and when ADETECT[1:0] are both 0). PERM_DRV should only be set to 1 if the FREEDM-84P672 is the only device driving the SBI ADD bus and it is desired to prevent the bus tristating.
FASTCLK Frequency 51.84 MHz 44.928 MHz Reserved 66 MHz
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x080 : GPIC Control Bit
Bit 31 to Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXH
RPWTH[5] RPWTH[4] RPWTH[3] RPWTH[2] RPWTH[1] RPWTH[0] Unused Unused Unused Unused PONS_E SOE_E LENDIAN Reserved
0 0 0 0 0 0 X X X X 0 0 1 0
This register configures the operation of the GPIC.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. Reserved: The Reserved bit must be set low for correct operation of the FREEDM84P672.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
LENDIAN: The Little Endian mode bit (LENDIAN) selects between Big Endian or Little Endian format when reading packet data from and writing packet data to PCI host memory. When LENDIAN is set low, Big Endian format is selected. When LENDIAN is set high, Little Endian format is selected. Descriptor references and the contents of descriptors are always transferred in Little Endian Format. Please refer below for each format's byte ordering.
Table 21 - Big Endian Format
00 DWORD Address 04 Bit 31 BYTE 0 BYTE 4 24 23 BYTE 1 BYTE 5 16 15 BYTE 2 BYTE 6 8 7 Bit 0 BYTE 3 BYTE 7
* * *
n-4 BYTE n-4
* * *
BYTE n-3
* * *
BYTE n-2
* * *
BYTE n-1
Table 22 - Little Endian Format
00 DWORD Address 04 Bit 31 BYTE 3 BYTE 7 24 23 BYTE 2 BYTE 6 16 15 BYTE 1 BYTE 5 8 7 Bit 0 BYTE 0 BYTE 4
* * *
n-4 BYTE n-1
* * *
BYTE n-2
* * *
BYTE n-3
* * *
BYTE n-4
SOE_E: The stop on error enable (SOE_E) bit determines the action the PCI controller will take when a system or parity error occurs. When set high the PCI controller will disconnect the PCI REQB signal from the PCI bus. This prevents the GPIC from the becoming a master device on the PCI bus in event of one of the following bits in the PCI Configuration Command/Status register being set: DPR, RTABT, MABT and SERR. When the SOE_E bit is set low the PCI controller will continue to allow master transactions on the PCI bus. Setting this bit low after an error has occurred or clearing the appropriate bit the PCI Configuration Command/Status register will reactivate the PCI REQB signal and allow the GPIC to resume servicing the local
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
masters. In the event of a system or parity error it is recommended that the core device be reset unless the cause of the fault can be determined. PONS_E: The Report PERR on SERR enable (PONS_E) bit controls the source of system errors. When set high all parity errors will be signaled to the host via the SERRB output signal. RPWTH[5:0]: The Receive Packet Write Threshold bits (RPWTH[5:0]) controls the amount of data in the write FIFO before the GPIC begins arbitrating for the bus. The GPIC will begin requesting access to the PCI bus when the number of dwords of packet data loaded by the RMAC672 reaches the threshold specified by RPWTH[5:0]. If the FREEDM-32P672 is being operated with PCICLK at a higher frequency than SYSCLK, RPWTH must be set to a value that ensures that the write FIFO does not underflow due to data being read out of the FIFO faster than data is written into the FIFO. It is recommended that RPWTH be set to a value not less than
[4 (XFER + 1)]e1 - SYSCLKfreq. u - erg SYSCLKfreq. u e ue u
e PCICLKfreq. u e PCICLKfreq. u where rg is the minimum number of clock cycles in which GNTB can be received after REQB has been asserted.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x100 : RCAS Indirect Link and Time-slot Select Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W
Type
Function
Unused
Default
XXXXH
BUSY RWB Unused LINK[6] LINK[5] LINK[4] LINK[3] LINK[2] LINK[1] LINK[0] Unused TSLOT[4] TSLOT[3] TSLOT[2] TSLOT[1] TSLOT[0]
X 0 X 0 0 0 0 0 0 0 X 0 0 0 0 0
This register provides the receive link and time-slot number used to access the channel provision RAM. Writing to this register triggers an indirect register access.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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TSLOT[4:0]: The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be configured or interrogated in the indirect access. For a channelised T1/J1 link, time-slots 1 to 24 are valid. For a channelised E1 link, time-slots 1 to 31 are valid. For unchannelised or unframed links, only time-slot 0 is valid. LINK[6:0]: The indirect link number bits (LINK[6:0]) select amongst the 84 receive links to be configured or interrogated in the indirect access. RWB: The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the channel provision RAM. The address to the channel provision RAM is constructed by concatenating the TSLOT[4:0] and LINK[4:0] bits. Writing a logic zero to RWB triggers an indirect write operation. Data to be written is taken from the PROV, the CDLBEN and the CHAN[9:0] bits of the RCAS Indirect Channel Data register. Writing a logic one to RWB triggers an indirect read operation. Addressing of the RAM is the same as in an indirect write operation. The data read can be found in the PROV, the CDLBEN and the CHAN[9:0] bits of the RCAS Indirect Channel Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the RCAS Indirect Channel Data register or to determine when a new indirect write operation may commence.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x104 : RCAS Indirect Channel Data Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 to Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
CDLBEN PROV Unused
0 0 XH
CHAN[9] CHAN[8] CHAN[7] CHAN[6] CHAN[5] CHAN[4] CHAN[3] CHAN[2] CHAN[1] CHAN[0]
0 0 0 0 0 0 0 0 0 0
This register contains the data read from the channel provision RAM after an indirect read operation or the data to be inserted into the channel provision RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. CHAN[9:0]: The indirect data bits (CHAN[9:0]) report the channel number read from the channel provision RAM after an indirect read operation has completed.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Channel number to be written to the channel provision RAM in an indirect write operation must be set up in this register before triggering the write. CHAN[9:0] reflects the value written until the completion of a subsequent indirect read operation. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the channel provision RAM after an indirect read operation has completed. The provision enable flag to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the current receive data byte is processed as part of the channel as indicated by CHAN[9:0]. When PROV is set low, the current time-slot does not belong to any channel and the receive data byte ignored. PROV reflects the value written until the completion of a subsequent indirect read operation. CDLBEN: The indirect channel based diagnostic loopback enable bit (CDLBEN) reports the loopback enable flag read from channel provision RAM after an indirect read operation has complete. The loopback enable flag to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When CDLBEN is set high, the current receive data byte is to be over-written by data retrieved from the loopback FIFO of the channel as indicated by CHAN[9:0]. When CDLBEN is set low, the current receive data byte is processed normally. CDLBEN reflects the value written until the completion of a subsequent indirect read operation.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x10C : RCAS Channel Disable Bit
Bit 31 to Bit 16 Bit 15 Bit 14 to Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
CHDIS Unused
0 XXH
DCHAN[9] DCHAN[8] DCHAN[7] DCHAN[6] DCHAN[5] DCHAN[4] DCHAN[3] DCHAN[2] DCHAN[1] DCHAN[0]
0 0 0 0 0 0 0 0 0 0
This register controls the disabling of one specific channel to allow orderly provisioning of time-slots associated with that channel.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. DCHAN[9:0]: The disable channel number bits (DCHAN[9:0]) selects the channel to be disabled. When CHDIS is set high, the channel specified by DCHAN[9:0] is disabled. Data in time-slots associated with the specified channel is ignored. When CHDIS is set low, the channel specified by DCHAN[9:0] operates normally.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
CHDIS: The channel disable bit (CHDIS) controls the disabling of the channels specified by DCHAN[9:0]. When CHDIS is set high, the channel selected by DCHAN[9:0] is disabled. Data in time-slots associated with the specified channel is ignored. When CHDIS is set low, the channel specified by DCHAN[9:0] operates normally.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x140 : RCAS SBI SPE1 Configuration Register #1 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
FEN[11] FEN[10] FEN[9] FEN[8] FEN[7] FEN[6] FEN[5] FEN[4] FEN[3] FEN[2] FEN[1] FEN[0] Unused SBI_MODE[2] SBI_MODE[1] SBI_MODE[0]
0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0
This register configures the operational mode of receive links 0, 3, 6, 9, ... 33, 36, 39, ...81, i.e. those links mapped to SPE 1 of the SBI DROP BUS.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SBI_MODE[2:0]: The SBI mode select bits (SBI_MODE[2:0]) configure the receive links of SPE1, as shown in the following table:
Table 23 - SBI Mode SPE1 Configuration SBI_MODE [2:0] 000 001 010 011 100 101 110 111
FEN[11:0] Each FEN bit, FEN[n], configures link 3n for framed operation. In unframed operation (FEN[n] = 0), all framing bit locations are treated as containing data. In framed mode (FEN[n] = 1), the contents of framing bit locations are ignored.
SPE1 Configuration Single unchannelised DS-3 on link 0 28 T1/J1 links 21 E1 links (links 63, 66, 69, ... , 81 are unused) Reserved Reserved Reserved Reserved Reserved
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x144 : RCAS SBI SPE1 Configuration Register #2 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
FEN[27] FEN[26] FEN[25] FEN[24] FEN[23] FEN[22] FEN[21] FEN[20] FEN[19] FEN[18] FEN[17] FEN[16] FEN[15] FEN[14] FEN[13] FEN[12]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The bits of this register set are used to configure the framing modes of receive links 36, 39, 42 ... 81.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
FEN[27:12]: Each FEN bit, FEN[n], configures link 3n for framed operation. In unframed operation (FEN[n] = 0), all framing bit locations are treated as containing data. In framed mode (FEN[n] = 1), the contents of framing bit locations are ignored.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x148 : RCAS SBI SPE2 Configuration Register #1 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
FEN[11] FEN[10] FEN[9] FEN[8] FEN[7] FEN[6] FEN[5] FEN[4] FEN[3] FEN[2] FEN[1] FEN[0] Unused SBI_MODE[2] SBI_MODE[1] SBI_MODE[0]
0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0
This register configures the operational mode of receive links 1, 4, 7, 10, ... 34, 37, ...82, i.e. those links mapped to SPE 2 of the SBI DROP BUS.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SBI_MODE[2:0]: The SBI mode select bits (SBI_MODE[2:0]) configure the receive links of SPE2, as shown in the following table:
Table 24 - SBI Mode SPE2 Configuration SBI_MODE [2:0] 000 001 010 011 100 101 110 111
FEN[11:0] Each FEN bit, FEN[n], configures link 3n+1 for framed operation. In unframed operation (FEN[n] = 0), all framing bit locations are treated as containing data. In framed mode (FEN[n] = 1), the contents of framing bit locations are ignored.
SPE2 Configuration Single unchannelised DS-3 on link 1 28 T1/J1 links 21 E1 links (links 64, 67, 70, ... , 82 are unused) Reserved Reserved Reserved Reserved Reserved
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x14C : RCAS SBI SPE2 Configuration Register #2 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
FEN[27] FEN[26] FEN[25] FEN[24] FEN[23] FEN[22] FEN[21] FEN[20] FEN[19] FEN[18] FEN[17] FEN[16] FEN[15] FEN[14] FEN[13] FEN[12]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The bits of this register set are used to configure the framing modes of receive links 37, 40, 43 ... 82.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
FEN[27:12]: Each FEN bit, FEN[n], configures link 3n+1 for framed operation. In unframed operation (FEN[n] = 0), all framing bit locations are treated as containing data. In framed mode (FEN[n] = 1), the contents of framing bit locations are ignored.
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138
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x150 : RCAS SBI SPE3 Configuration Register #1 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
FEN[11] FEN[10] FEN[9] FEN[8] FEN[7] FEN[6] FEN[5] FEN[4] FEN[3] FEN[2] FEN[1] FEN[0] Unused SBI_MODE[2] SBI_MODE[1] SBI_MODE[0]
0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0
This register configures the operational mode of receive links 2, 5, 8, 11, ... 35, 38, ...83, i.e. those links mapped to SPE 3 of the SBI DROP BUS.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SBI_MODE[2:0]: The SBI mode select bits (SBI_MODE[2:0]) configure the receive links of SPE3, as shown in the following table:
Table 25 - SBI Mode SPE3 Configuration SBI_MODE [2:0] 000 001 010 011 100 101 110 111
FEN[11:0] Each FEN bit, FEN[n], configures link 3n+2 for framed operation. In unframed operation (FEN[n] = 0), all framing bit locations are treated as containing data. In framed mode (FEN[n] = 1), the contents of framing bit locations are ignored.
SPE3 Configuration Single unchannelised DS-3 on link 2 28 T1/J1 links 21 E1 links (links 65, 68, 71, ... , 83 are unused) Reserved Reserved Reserved Reserved Reserved
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x154 : RCAS SBI SPE3 Configuration Register #2 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
FEN[27] FEN[26] FEN[25] FEN[24] FEN[23] FEN[22] FEN[21] FEN[20] FEN[19] FEN[18] FEN[17] FEN[16] FEN[15] FEN[14] FEN[13] FEN[12]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The bits of this register set are used to configure the framing modes of receive links 38, 41, 44 ... 83.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
FEN[27:12]: Each FEN bit, FEN[n], configures link 3n+2 for framed operation. In unframed operation (FEN[n] = 0), all framing bit locations are treated as containing data. In framed mode (FEN[n] = 1), the contents of framing bit locations are ignored.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x180 - 0x188 : RCAS Links #0 to #2 Configuration Bit
Bit 31 to Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXXH
Reserved Unused Reserved Reserved Reserved
0 X 0 0 0
This register controls the operation of receive links #0 to #2 when they are configured to receive data from the RD[2:0] inputs (i.e. SPEn_EN is low).
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. Reserved: The reserved bits must be set low for correct operation of the FREEDM84P672 device.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x200 : RHDL Indirect Channel Select Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 to Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W
Type
Function
Unused
Default
XXXXH
BUSY CRWB Unused
X 0 XH
CHAN[9] CHAN[8] CHAN[7] CHAN[6] CHAN[5] CHAN[4] CHAN[3] CHAN[2] CHAN[1] CHAN[0]
0 0 0 0 0 0 0 0 0 0
This register provides the channel number used to access the receive channel provision RAM. Writing to this register triggers an indirect channel register access.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. CHAN[9:0]: The indirect channel number bits (CHAN[9:0]) indicate the receive channel to be configured or interrogated in the indirect access.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
CRWB: The channel indirect access control bit (CRWB) selects between a configure (write) or interrogate (read) access to the receive channel provision RAM. Writing a logic zero to CRWB triggers an indirect write operation. Data to be written is taken from the Indirect Channel Data registers. Writing a logic one to CRWB triggers an indirect read operation. The data read can be found in the Indirect Channel Data registers. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the RHDL Indirect Channel Data #1 and #2 registers or to determine when a new indirect write operation may commence.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x204 : RHDL Indirect Channel Data Register #1 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R W W W W W W W W W W W W
Type
Function
Unused
Default
XXXXH
PROV STRIP DELIN TAVAIL Reserved FPTR[10] FPTR[9] FPTR[8] FPTR[7] FPTR[6] FPTR[5] FPTR[4] FPTR[3] FPTR[2] FPTR[1] FPTR[0]
0 0 0 X X X X X X X X X X X X X
This register contains data read from the channel provision RAM after an indirect read operation or data to be inserted into the channel provision RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
FPTR[10:0]: The indirect FIFO block pointer (FPTR[10:0]) identifies one of the blocks of the circular linked list in the partial packet buffer used in the logical FIFO of the current channel. The FIFO pointer to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. The FIFO pointer value can be any one of the blocks provisioned to form the circular buffer. Reserved: The reserved bit must be set low for correct operation of the FREEDM84P672 device. TAVAIL: The indirect transaction available bit (TAVAIL) reports the fill level of the partial packet buffer used in the logical FIFO of the current channel. TAVAIL is set high when the FIFO of the current channel contains sufficient data, as controlled by XFER[3:0], to request a DMA transfer to the host memory. TAVAIL is set low when the amount of receive data is too small to require a transfer to host memory. TAVAIL is updated by an indirect channel read operation. DELIN: The indirect delineate enable bit (DELIN) configures the HDLC processor to perform flag sequence delineation and bit de-stuffing on the incoming data stream. The delineate enable bit to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When DELIN is set high, flag sequence delineation and bit de-stuffing is performed on the incoming data stream. When DELIN is set low, the HDLC processor does not perform any processing (flag sequence delineation, bit de-stuffing nor CRC verification) on the incoming stream. DELIN reflects the value written until the completion of a subsequent indirect channel read operation. STRIP: The indirect frame check sequence discard bit (STRIP) configures the HDLC processor to remove the CRC from the incoming frame when writing the data to the channel FIFO. The FCS discard bit to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When STRIP is set high and CRC[1:0] is not equal to "00", the received CRC value is not written to the FIFO. When STRIP is set low, the received CRC value is written to the FIFO. The bytes in buffer field of the RPD correctly reflect the presence/absence of CRC bytes in the buffer. The value of STRIP is ignored when DELIN is low. STRIP reflects
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
the value written until the completion of a subsequent indirect channel read operation. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the channel provision RAM after an indirect channel read operation has completed. The provision enable flag to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the HDLC processor will process data on the channel specified by CHAN[9:0]. When PROV is set low, the HDLC processor will ignore data on the channel specified by CHAN[9:0]. PROV reflects the value written until the completion of a subsequent indirect channel read operation.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x208 : RHDL Indirect Channel Data Register #2 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
7BIT PRIORITY INVERT Unused CRC[1] CRC[0] OFFSET[1] OFFSET[0] Unused Unused Unused Unused XFER[3] XFER[2] XFER[1] XFER[0]
0 0 0 X 0 0 0 0 X X X X 0 0 0 0
This register contains data read from the channel provision RAM after an indirect read operation or data to be inserted into the channel provision RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
XFER[3:0]: The indirect channel transfer size (XFER[3:0]) configures the amount of data transferred in each transaction. The channel transfer size to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When the channel FIFO depth reaches the depth specified by XFER[3:0] or when an end-of-packet exists in the FIFO, a request will be made to the RMAC672 to initiate a PCI write access to transfer the data to the PCI host. Channel transfer size is measured in 16 byte blocks. The amount of data transferred and the depth threshold are specified by given setting is: XFER[3:0] + 1 blocks = 16 * (XFER[3:0] + 1) bytes XFER[3:0] should be set such that the number of blocks transferred is at least two fewer than the total allocated to the associated channel. XFER[3:0] reflects the value written until the completion of a subsequent indirect channel read operation. OFFSET[1:0]: The packet byte offset (OFFSET[1:0]) configures the partial packet processor to insert invalid bytes at the beginning of a packet stored in the channel FIFO. The value of OFFSET[1:0] to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. The number of bytes inserted before the beginning of a HDLC packet is defined by the binary value of OFFSET[1:0]. OFFSET[1:0] reflects the value written until the completion of a subsequent indirect channel read operation. CRC[1:0]: The CRC algorithm bits (CRC[1:0]) configures the HDLC processor to perform CRC verification on the incoming data stream. The value of CRC[1:0] to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. CRC[1:0] is ignored when DELIN is low. CRC[1:0] reflects the value written until the completion of a subsequent indirect channel read operation.
Table 26 - CRC[1:0] Settings CRC[1]
0 0 1
CRC[0]
0 1 0
Operation
No Verification CRC-CCITT CRC-32
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
CRC[1]
1 INVERT:
CRC[0]
1
Operation
Reserved
The HDLC data inversion bit (INVERT) configures the HDLC processor to logically invert the incoming HDLC stream from the RCAS672 before processing it. The value of INVERT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When INVERT is set to one, the HDLC stream is logically inverted before processing. When INVERT is set to zero, the HDLC stream is not inverted before processing. INVERT reflects the value written until the completion of a subsequent indirect channel read operation. PRIORITY: The channel FIFO priority bit (PRIORITY) informs the partial packet processor that the channel has precedence over other channels when being serviced by the RMAC672 block for transfer to the PCI host. The value of PRIORITY to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. Channel FIFOs with PRIORITY set to one are serviced by the RMAC672 before channel FIFOs with PRIORITY set to zero. Channels with an HDLC data rate to FIFO size ratio that is significantly higher than other channels should have PRIORITY set to one. PRIORITY reflects the value written until the completion of a subsequent indirect channel read operation. 7BIT: The 7BIT enable bit (7BIT) configures the HDLC processor to ignore the least significant bit of each octet in the incoming channel stream. The value of 7BIT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When 7BIT is set high, the least significant bit (last bit of each octet received), is ignored. When 7BIT is set low, the entire receive data stream is processed. 7BIT reflects the value written until the completion of a subsequent indirect channel read operation.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x210 : RHDL Indirect Block Select Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W
Type
Function
Unused
Default
XXXXH
BUSY BRWB Unused Unused Reserved BLOCK[10] BLOCK[9] BLOCK[8] BLOCK[7] BLOCK[6] BLOCK[5] BLOCK[4] BLOCK[3] BLOCK[2] BLOCK[1] BLOCK[0]
X X X X X X X X X X X X X X X X
This register provides the block number used to access the block pointer RAM. Writing to this register triggers an indirect block register access.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
BLOCK[10:0]: The indirect block number (BLOCK[10:0]) indicate the block to be configured or interrogated in the indirect access. Reserved: The reserved bit must be set low for correct operation of the FREEDM84P672 device. BRWB: The block indirect access control bit (BRWB) selects between a configure (write) or interrogate (read) access to the block pointer RAM. Writing a logic zero to BRWB triggers an indirect block write operation. Data to be written is taken from the Indirect Block Data register. Writing a logic one to BRWB triggers an indirect block read operation. The data read can be found in the Indirect Block Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the RHDL Indirect Block Data register or to determine when a new indirect write operation may commence.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x214 : RHDL Indirect Block Data Bit
Bit 31 to Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXH
Reserved BPTR[10] BPTR[9] BPTR[8] BPTR[7] BPTR[6] BPTR[5] BPTR[4] BPTR[3] BPTR[2] BPTR[1] BPTR[0]
X 0 0 0 0 0 0 0 0 0 0 0
This register contains data read from the block pointer RAM after an indirect block read operation or data to be inserted into the block pointer RAM in an indirect block write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. BPTR[10:0]: The indirect block pointer (BPTR[10:0]) configures the block pointer of the block specified by the Indirect Block Select register. The block pointer to be written to the block pointer RAM, in an indirect write operation, must be set up in this register before triggering the write. The block pointer value is the block number of the next block in the linked list. A circular list of blocks must be formed in order to use the block list as a receive channel FIFO buffer.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
BPTR[10:0] reflects the value written until the completion of a subsequent indirect block read operation. When provisioning a channel FIFO, all block pointers must be re-written to properly initialize the FIFO. Reserved: The reserved bit must be set low for correct operation of the FREEDM84P672 device.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x220 : RHDL Configuration Bit
Bit 31 to Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W
Type
Function
Unused
Default
XXXXXXH
LENCHK TSTD Unused Unused Unused Unused Unused Unused Unused Unused
0 0 X X X X X X X X
This register configures all provisioned receive channels.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. TSTD: The telecom standard bit (TSTD) controls the bit ordering of the HDLC data transferred to the PCI host. When TSTD is set low, the least significant bit of the each byte on the PCI bus (AD[0], AD[8], AD[16] and AD[24]) is the first HDLC bit received and the most significant bit of each byte (AD[7], AD[15], AD[23] and AD[31]) is the last HDLC bit received (datacom standard). When TSTD is set high, AD[0], AD[8], AD[16] and AD[24] are the last HDLC bit received and AD[7], AD[15], AD[23] and AD[31] are the first HDLC bit received (telecom standard).
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
LENCHK: The packet length error check bit (LENCHK) controls the checking of receive packets that are longer than the maximum programmed length. When LENCHK is set high, receive packets are aborted and the remainder of the frame discarded when the packet exceeds the maximum packet length given by MAX[15:0]. When LENCHK is set low, receive packets are not checked for maximum size and MAX[15:0] must be set to 'hFFFF.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x224 : RHDL Maximum Packet Length Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
MAX[15] MAX[14] MAX[13] MAX[12] MAX[11] MAX[10] MAX[9] MAX[8] MAX[7] MAX[6] MAX[5] MAX[4] MAX[3] MAX[2] MAX[1] MAX[0]
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
This register configures the maximum legal HDLC packet byte length.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. MAX[15:0]: The maximum HDLC packet length (MAX[15:0]) configures the FREEDM84P672 to reject HDLC packets longer than a maximum size when LENCHK
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
is set high. Receive packets with total length, including address, control, information and FCS fields, greater than MAX[15:0] bytes are aborted. When LENCHK is set low, aborts are not generated regardless of packet length and MAX[15:0] must be set to 'hFFFF.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x280 : RMAC Control Bit
Bit 31 to Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXH
Reserved RPQ_SFN[1] RPQ_SFN[0] RPQ_LFN[1] RPQ_LFN[0] RPQ_RDYN[2] RPQ_RDYN[1] RPQ_RDYN[0] RAWMAX[1] RAWMAX[0] SCACHE LCACHE ENABLE
0 0 0 0 0 0 0 0 1 1 1 1 0
This register configures the RMAC672 block.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. ENABLE: The ENABLE bit determines whether or not the RMAC672 accepts data from the RHDL672 block and sends it to host memory. When set to 1, these tasks are enabled. When set to 0, they are disabled.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
LCACHE: The large buffer cache enable bit (LCACHE) enables caching of Large Buffer RPDRs. When LCACHE is set high, RPDRs are fetched from the RPDR Large Buffer Free Queue in groups of up to six. When LCACHE is set low, RPDRs are fetched one at a time. SCACHE: The small buffer cache enable bit (SCACHE) enables caching of Small Buffer RPDRs. When SCACHE is set high, RPDRs are fetched from the RPDR Small Buffer Free Queue in groups of up to six. When SCACHE is set low, RPDRs are fetched one at a time. RAWMAX[1:0]: The RAWMAX[1:0] field determines how `raw' (i.e. non packet delimited) data is written to host memory. Raw data is written to buffers in host memory in the same manner as packet delimited data. Whenever RAWMAX[1:0] + 1 buffers have been filled, the resulting buffer chain is placed in the ready queue. RPQ_RDYN[2:0]: The RPQ_RDYN[2:0] field sets the number of receive packet descriptor references (RPDRs) that must be placed onto the RPDR ready queue before the RPDR ready interrupt (RPQRDYI) is asserted, as follows:
Table 27 - RPQ_RDYN[2:0] settings RPQ_RDYN[2:0]
000 001 010 011 100 101 110 111
No of RPDRs
1 4 6 8 16 32 Reserved Reserved
If the value of RPQ_RDYN[2:0] is altered, the new value does not become effective until after the RPQRDYI interrupt is next generated.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RPQ_LFN[1:0]: The RPQ_LFN[1:0] field sets the number of times that a block of RPDRs are read from the Large Buffer Free Queue to the RMAC672s internal cache before the RPDR Large Buffer Free Queue interrupt (RPQLFI) is asserted, as follows:
Table 28 - RPQ_LFN[1:0] Settings RPQ_LFN[1:0]
00 01 10 11
No of Reads
1 4 8 Reserved
If the value of RPQ_LFN[1:0] is altered, the new value does not become effective until after the RPQLFI interrupt is next generated. RPQ_SFN[1:0]: The RPQ_SFN[1:0] field sets the number of times that a block of RPDRs are read from the Small Buffer Free Queue to the RMAC672s internal cache before the RPDR Small Buffer Free Queue interrupt (RPQSFI) is asserted, as follows:
Table 29 - RPQ_SFN[1:0] Settings RPQ_SFN[1:0]
00 01 10 11
No of Reads
1 4 8 Reserved
If the value of RPQ_SFN[1:0] is altered, the new value does not become effective until after the RPQSFI interrupt is next generated. Reserved: The reserved bit must be set low for correct operation of the FREEDM84P672 device.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x284 : RMAC Indirect Channel Provisioning Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 to Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W
Type
Function
Unused
Default
XXXXH
BUSY RWB Unused
X 0 XH
PROV CHAN[9] CHAN[8] CHAN[7] CHAN[6] CHAN[5] CHAN[4] CHAN[3] CHAN[2] CHAN[1] CHAN[0]
0 0 0 0 0 0 0 0 0 0 0
The Channel Provisioning Register is used to temporarily unprovision channels, and also to query the provision status of channels. Channel is permanently provisioned and can only be unprovisioned transiently. When a channel is unprovisioned, a partially received packet, if any, will be flushed and marked as unprovisioned in the RPDRR queue status field. The channel then returns to being provisioned automatically.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
CHAN[9:0]: The indirect data bits (CHAN[9:0]) report the channel number read from the RMAC672 internal memory after an indirect read operation has completed. Channel number to be written to the RMAC672 internal memory in an indirect write operation must be set up in this register before triggering the write. CHAN[9:0] reflects the value written until the completion of a subsequent indirect read operation. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the RMAC672 internal memory after an indirect read operation has completed. The provision enable flag to be written to the RMAC672 internal memory, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the channel indicated by CHAN[9:0] is provisioned. When PROV is set low, the channel indicated by CHAN[9:0] is unprovisioned temporarily. Any partially received packets are flushed and the status in the RPDRR queue is marked unprovisioned. The channel then returns to being provisioned and PROV will report a logic high after the next indirect read operation. PROV reflects the value written until the completion of a subsequent indirect read operation. RWB: The Read/Write Bar (RWB) bit selects between a provisioning/unprovisioning operation (write) or a query operation (read). Writing a logic 0 to RWB triggers the provisioning or unprovisioning of a channel as specified by CHAN[9:0] and PROV. Writing a logic 1 to RWB triggers a query of the channel specified by CHAN[9:0]. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available or to determine when a new indirect write operation may commence.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x288 : RMAC Packet Descriptor Table Base LSW Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDTB[15] RPDTB[14] RPDTB[13] RPDTB[12] RPDTB[11] RPDTB[10] RPDTB[9] RPDTB[8] RPDTB[7] RPDTB[6] RPDTB[5] RPDTB[4] RPDTB[3] RPDTB[2] RPDTB[1] RPDTB[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the less significant word of the Receive Descriptor Table Base address. The contents of this register is held in a holding register until a write access to the companion RMAC Receive Descriptor Table Base MSW register.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x28C : RMAC Packet Descriptor Table Base MSW Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDTB[31] RPDTB[30] RPDTB[29] RPDTB[28] RPDTB[27] RPDTB[26] RPDTB[25] RPDTB[24] RPDTB[23] RPDTB[22] RPDTB[21] RPDTB[20] RPDTB[19] RPDTB[18] RPDTB[17] RPDTB[16]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the more significant word of the Receive Descriptor Table Base address. The contents of the companion RMAC Receive Descriptor Table Base LSW register is held in a holding register until a write access to this register, at which point, the base address of the receive packet descriptor table is updated.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RPDTB[31:0]: The receive packet descriptor table base bits (RPDTB[31:0]) provides the base address of the Receive Packet Descriptor Table in PCI host memory. This register is initialised by the host. To calculate the physical address of a RPD, the 15 bit RPD offset must be added to bits 31 to 4 of the Receive Packet Descriptor Table Base (RPDTB[31:4]). The table must be on a 16 byte boundary and thus the least significant four bits must be written to logic zero.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x290 : RMAC Queue Base LSW Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RQB[15] RQB[14] RQB[13] RQB[12] RQB[11] RQB[10] RQB[9] RQB[8] RQB[7] RQB[6] RQB[5] RQB[4] RQB[3] RQB[2] RQB[1] RQB[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the less significant word of the Receive Queue Base address. The contents of this register is held in a holding register until a write access to the companion RMAC Receive Queue Base MSW register.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x294 : RMAC Queue Base MSW Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RQB[31] RQB[30] RQB[29] RQB[28] RQB[27] RQB[26] RQB[25] RQB[24] RQB[23] RQB[22] RQB[21] RQB[20] RQB[19] RQB[18] RQB[17] RQB[16]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the more significant word of the Receive Queue Base address. The contents of the companion RMAC Receive Queue Base LSW register is held in a holding register until a write access to this register, at which point, the base address of the receive queue is updated.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RQB[31:0]: The receive queue base bits (RQB[31:0]) provides the base address of the Large Buffer RPDR Free, Small Buffer RPDR Free and RPDR Ready queues in PCI host memory. This register is initialised by the host. To calculate the physical address of a particular receive queue element, the RQB bits are added with the appropriate queue start, end, read or write index registers to form the physical address. The base address must be dword aligned and thus the least significant two bits must be written to logic zero.
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170
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x298 : RMAC Packet Descriptor Reference Large Buffer Free Queue Start Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDRLFQS[15] RPDRLFQS[14] RPDRLFQS[13] RPDRLFQS[12] RPDRLFQS[11] RPDRLFQS[10] RPDRLFQS[9] RPDRLFQS[8] RPDRLFQS[7] RPDRLFQS[6] RPDRLFQS[5] RPDRLFQS[4] RPDRLFQS[3] RPDRLFQS[2] RPDRLFQS[1] RPDRLFQS[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Packet Descriptor Reference Large Buffer Free Queue start address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RPDRLFQS[15:0]: The receive packet descriptor reference (RPDR) large buffer free queue start bits (RPDRLFQS[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Large Buffer Free Queue start address. This register is initialised by the host. The physical start address of the RPDRLF queue is the sum of RPDRLFQS[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x29C : RMAC Packet Descriptor Reference Large Buffer Free Queue Write Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDRLFQW[15] RPDRLFQW[14] RPDRLFQW[13] RPDRLFQW[12] RPDRLFQW[11] RPDRLFQW[10] RPDRLFQW[9] RPDRLFQW[8] RPDRLFQW[7] RPDRLFQW[6] RPDRLFQW[5] RPDRLFQW[4] RPDRLFQW[3] RPDRLFQW[2] RPDRLFQW[1] RPDRLFQW[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Packet Descriptor Reference Large Buffer Free Queue write address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
173
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2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. RPDRLFQW[15:0]: The receive packet descriptor reference (RPDR) large buffer free queue write bits (RPDRLFQW[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Large Buffer Free Queue write pointer. This register is initialised by the host. The physical write address in the RPDRLF queue is the sum of RPDRLFQW[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
174
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x2A0 : RMAC Packet Descriptor Reference Large Buffer Free Queue Read Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDRLFQR[15] RPDRLFQR[14] RPDRLFQR[13] RPDRLFQR[12] RPDRLFQR[11] RPDRLFQR[10] RPDRLFQR[9] RPDRLFQR[8] RPDRLFQR[7] RPDRLFQR[6] RPDRLFQR[5] RPDRLFQR[4] RPDRLFQR[3] RPDRLFQR[2] RPDRLFQR[1] RPDRLFQR[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Packet Descriptor Reference Large Buffer Free Queue read address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. RPDRLFQR[15:0]: The receive packet descriptor reference (RPDR) large buffer free queue read bits (RPDRLFQR[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Large Buffer Free Queue read pointer. This register is initialised by the host. The physical read address in the RPDRLF queue is the sum of RPDRLFQR[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
176
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x2A4 : RMAC Packet Descriptor Reference Large Buffer Free Queue End Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDRLFQE[15] RPDRLFQE[14] RPDRLFQE[13] RPDRLFQE[12] RPDRLFQE[11] RPDRLFQE[10] RPDRLFQE[9] RPDRLFQE[8] RPDRLFQE[7] RPDRLFQE[6] RPDRLFQE[5] RPDRLFQE[4] RPDRLFQE[3] RPDRLFQE[2] RPDRLFQE[1] RPDRLFQE[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Packet Descriptor Reference Large Buffer Free Queue end address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RPDRLFQE[15:0]: The receive packet descriptor reference (RPDR) large buffer free queue end bits (RPDRLFQE[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Large Buffer Free Queue end address. This register is initialised by the host. The physical end address in the RPDRLF queue is the sum of RPDRLFQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
178
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x2A8 : RMAC Packet Descriptor Reference Small Buffer Free Queue Start Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDRSFQS[15] RPDRSFQS[14] RPDRSFQS[13] RPDRSFQS[12] RPDRSFQS[11] RPDRSFQS[10] RPDRSFQS[9] RPDRSFQS[8] RPDRSFQS[7] RPDRSFQS[6] RPDRSFQS[5] RPDRSFQS[4] RPDRSFQS[3] RPDRSFQS[2] RPDRSFQS[1] RPDRSFQS[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Packet Descriptor Reference Small Buffer Free Queue start address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RPDRSFQS[15:0]: The receive packet descriptor reference (RPDR) small buffer free queue start bits (RPDRSFQS[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Small Buffer Free Queue start address. This register is initialised by the host. The physical start address of the RPDRSF queue is the sum of RPDRSFQS[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register.
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180
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x2AC : RMAC Packet Descriptor Reference Small Buffer Free Queue Write Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDRSFQW[15] RPDRSFQW[14] RPDRSFQW[13] RPDRSFQW[12] RPDRSFQW[11] RPDRSFQW[10] RPDRSFQW[9] RPDRSFQW[8] RPDRSFQW[7] RPDRSFQW[6] RPDRSFQW[5] RPDRSFQW[4] RPDRSFQW[3] RPDRSFQW[2] RPDRSFQW[1] RPDRSFQW[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Packet Descriptor Reference Small Buffer Free Queue write address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. RPDRSFQW[15:0]: The receive packet descriptor reference (RPDR) small buffer free queue write bits (RPDRSFQW[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Small Buffer Free Queue write pointer. This register is initialised by the host. The physical write address in the RPDRSF queue is the sum of RPDRSFQW[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register.
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182
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x2B0 : RMAC Packet Descriptor Reference Small Buffer Free Queue Read Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDRSFQR[15] RPDRSFQR[14] RPDRSFQR[13] RPDRSFQR[12] RPDRSFQR[11] RPDRSFQR[10] RPDRSFQR[9] RPDRSFQR[8] RPDRSFQR[7] RPDRSFQR[6] RPDRSFQR[5] RPDRSFQR[4] RPDRSFQR[3] RPDRSFQR[2] RPDRSFQR[1] RPDRSFQR[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Packet Descriptor Reference Small Buffer Free Queue read address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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183
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. RPDRSFQR[15:0]: The receive packet descriptor reference (RPDR) small buffer free queue read bits (RPDRSFQR[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Small Buffer Free Queue read pointer. This register is initialised by the host. The physical read address in the RPDRSF queue is the sum of RPDRSFQR[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
184
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x2B4 : RMAC Packet Descriptor Reference Small Buffer Free Queue End Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDRSFQE[15] RPDRSFQE[14] RPDRSFQE[13] RPDRSFQE[12] RPDRSFQE[11] RPDRSFQE[10] RPDRSFQE[9] RPDRSFQE[8] RPDRSFQE[7] RPDRSFQE[6] RPDRSFQE[5] RPDRSFQE[4] RPDRSFQE[3] RPDRSFQE[2] RPDRSFQE[1] RPDRSFQE[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Packet Descriptor Reference Small Buffer Free Queue end address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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185
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RPDRSFQE[15:0]: The receive packet descriptor reference (RPDR) small buffer free queue end bits (RPDRSFQE[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Small Buffer Free Queue end address. This register is initialised by the host. The physical end address in the RPDRSF queue is the sum of RPDRSFQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
186
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x2B8 : RMAC Packet Descriptor Reference Ready Queue Start Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDRRQS[15] RPDRRQS[14] RPDRRQS[13] RPDRRQS[12] RPDRRQS[11] RPDRRQS[10] RPDRRQS[9] RPDRRQS[8] RPDRRQS[7] RPDRRQS[6] RPDRRQS[5] RPDRRQS[4] RPDRRQS[3] RPDRRQS[2] RPDRRQS[1] RPDRRQS[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Packet Descriptor Reference Ready Queue start address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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187
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RPDRRQS[15:0]: The receive packet descriptor reference (RPDR) ready queue start bits (RPDRRQS[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Ready Queue start address. This register is initialised by the host. The physical start address of the RPDRR queue is the sum of RPDRRQS[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register.
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188
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x2BC : RMAC Packet Descriptor Reference Ready Queue Write Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDRRQW[15] RPDRRQW[14] RPDRRQW[13] RPDRRQW[12] RPDRRQW[11] RPDRRQW[10] RPDRRQW[9] RPDRRQW[8] RPDRRQW[7] RPDRRQW[6] RPDRRQW[5] RPDRRQW[4] RPDRRQW[3] RPDRRQW[2] RPDRRQW[1] RPDRRQW[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Packet Descriptor Reference Ready Queue write address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart.
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189
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RPDRRQW[15:0]: The receive packet descriptor reference (RPDR) ready queue write bits (RPDRRQW[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Ready Queue write pointer. This register is initialised by the host. The physical write address in the RPDRR queue is the sum of RPDRRQW[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register.
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190
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x2C0 : RMAC Packet Descriptor Reference Ready Queue Read Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDRRQR[15] RPDRRQR[14] RPDRRQR[13] RPDRRQR[12] RPDRRQR[11] RPDRRQR[10] RPDRRQR[9] RPDRRQR[8] RPDRRQR[7] RPDRRQR[6] RPDRRQR[5] RPDRRQR[4] RPDRRQR[3] RPDRRQR[2] RPDRRQR[1] RPDRRQR[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Packet Descriptor Reference Ready Queue read address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart.
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191
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RPDRRQR[15:0]: The receive packet descriptor reference (RPDR) ready queue read bits (RPDRRQR[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Ready Queue read pointer. This register is initialised by the host. The physical read address in the RPDRR queue is the sum of RPDRRQR[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register.
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192
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x2C4 : RMAC Packet Descriptor Reference Ready Queue End Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
RPDRRQE[15] RPDRRQE[14] RPDRRQE[13] RPDRRQE[12] RPDRRQE[11] RPDRRQE[10] RPDRRQE[9] RPDRRQE[8] RPDRRQE[7] RPDRRQE[6] RPDRRQE[5] RPDRRQE[4] RPDRRQE[3] RPDRRQE[2] RPDRRQE[1] RPDRRQE[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Packet Descriptor Reference Ready Queue end address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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193
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
RPDRRQE[15:0]: The receive packet descriptor reference (RPDR) ready queue end bits (RPDRRQE[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Ready Queue end address. This register is initialised by the host. The physical end address in the RPDRR queue is the sum of RPDRRQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register.
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194
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x300 : TMAC Control Bit
Bit 31 to Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXH
FQFLUSH TDQ_FRN[1] TDQ_FRN[0] TDQ_RDYN[2] TDQ_RDYN[1] TDQ_RDYN[0] CACHE ENABLE
0 0 0 0 0 0 1 0
This register provides control of the TMAC672 block.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. ENABLE: The transmit DMA controller enable bit (ENABLE) enables the TMAC672 to accept TDRs from the TDR Ready Queue and reads packet data from host memory. When ENABLE is set high, the TMAC672 is enabled. When ENABLE is set low, the TDR Ready Queue is ignored. Once all linked lists of TDs built up by the TMAC672 have been exhausted, no more data will be transmitted on the TD[31:0] links. CACHE: The transmit descriptor reference cache enable bit (CACHE) controls the frequency at which TDRs are written to the TDR Free Queue. When CACHE is set high, freed TDRs are cached and then written up to six at a time. When CACHE is set low, freed TDRs are written one at a time.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TDQ_RDYN[2:0]: The TDQ_RDYN[2:0] field sets the number of transmit descriptor references (TDRs) that must be read from the TDR Ready Queue before the TDR Ready interrupt (TDQRDYI) is asserted, as follows:
Table 30 - TDQ_RDYN[2:0] Settings TDQ_RDYN[2:0]
000 001 010 011 100 101 110 111 TDQ_FRN[1:0]: The TDQ_FRN[1:0] field sets the number of times that a block of TDRs are written to the TDR Free Queue from the TMAC672s internal cache before the TDR Free Queue Interrupt (TDQFI) is asserted, as follows:
No of TDRs
1 4 6 8 16 32 Reserved Reserved
Table 31 - TDQ_FRN[1:0] Settings TDQ_FRN[1:0]
00 01 10 11 FQFLUSH: The Free Queue Flush bit (FQFLUSH) may be used to initiate a dump of the free queue cache retained locally within the TMAC672 to the free queue located in PCI host memory. When the FQFLUSH bit is set high, the TMAC672 dumps the contents of the free queue cache to the free queue in PCI host memory. The FQFLUSH bit is self clearing and will reset to zero when the flush is complete. Setting the FQFLUSH bit to zero has no affect.
No of Reads
1 4 8 Reserved
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196
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x304 : TMAC Indirect Channel Provisioning Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 to Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W
Type
Function
Unused
Default
XXXXH
BUSY RWB PROV Unused
X 0 0 XH
CHAN[9] CHAN[8] CHAN[7] CHAN[6] CHAN[5] CHAN[4] CHAN[3] CHAN[2] CHAN[1] CHAN[0]
0 0 0 0 0 0 0 0 0 0
The Channel Provisioning Register is used to provision and unprovision channels, and also to query the provision status of channels. When a channel is provisioned, chains of packet data for that channel will be accepted by the TMAC672 and placed on the channel's linked list of packets to be transmitted. When a channel is unprovisioned, chains of packet data for that channel will be rejected by the TMAC672 and returned to the TDR Free Queue with the status bits in the queue element set to indicate the rejection.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
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197
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
implemented. However, when all four byte enables are negated, no access is made to this register. CHAN[9:0]: The indirect data bits (CHAN[9:0]) report the channel number read from the TMAC672 internal memory after an indirect read operation has completed. Channel number to be written to the TMAC672 internal memory in an indirect write operation must be set up in this register before triggering the write. CHAN[9:0] reflects the value written until the completion of a subsequent indirect read operation. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the TMAC672 internal memory after an indirect read operation has completed. The provision enable flag to be written to the TMAC672 internal memory, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the channel as indicated by CHAN[9:0] is provisioned. When PROV is set low, the channel indicated by CHAN[9:0] is unprovisioned. PROV reflects the value written until the completion of a subsequent indirect read operation. RWB: The Read/Write Bar (RWB) bit selects between a provisioning/unprovisioning operation (write) or a query operation (read). Writing a logic 0 to RWB triggers the provisioning or unprovisioning of a channel as specified by CHAN[9:0] and PROV. Writing a logic 1 to RWB triggers a query of the channel specified by CHAN[9:0]. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available or to determine when a new indirect write operation may commence.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x308 : TMAC Descriptor Table Base LSW Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TDTB[15] TDTB[14] TDTB[13] TDTB[12] TDTB[11] TDTB[10] TDTB[9] TDTB[8] TDTB[7] TDTB[6] TDTB[5] TDTB[4] TDTB[3] TDTB[2] TDTB[1] TDTB[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the less significant word of the Transmit Descriptor Table Base address. The contents of this register is held in a holding register until a write access to the companion TMAC Transmit Descriptor Table Base MSW register.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x30C : TMAC Descriptor Table Base MSW Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TDTB[31] TDTB[30] TDTB[29] TDTB[28] TDTB[27] TDTB[26] TDTB[25] TDTB[24] TDTB[23] TDTB[22] TDTB[21] TDTB[20] TDTB[19] TDTB[18] TDTB[17] TDTB[16]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the more significant word of the Transmit Descriptor Table Base address. The contents of the companion TMAC Transmit Descriptor Table Base LSW register is held in a holding register until a write access to this register, at which point, the base address of the transmit descriptor table is updated.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 200
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TDTB[31:0]: The transmit descriptor table base bits (TDTB[31:0]) provides the base address of the Transmit Descriptor Table in PCI host memory. This register is initialised by the host. To calculate the physical address of a TD, the 15 bit TD offset must be added to bits 31 to 4 of the Transmit Descriptor Table Base (TDTB[31:4]). The table must be on a 16 byte boundary and thus the least significant four bits must be written to logic zero.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
201
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x310 : TMAC Queue Base LSW Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TQB[15] TQB[14] TQB[13] TQB[12] TQB[11] TQB[10] TQB[9] TQB[8] TQB[7] TQB[6] TQB[5] TQB[4] TQB[3] TQB[2] TQB[1] TQB[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the less significant word of the Transmit Queue Base address. The contents of this register is held in a holding register until a write access to the companion TMAC Transmit Queue Base MSW register.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x314 : TMAC Queue Base MSW Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TQB[31] TQB[30] TQB[29] TQB[28] TQB[27] TQB[26] TQB[25] TQB[24] TQB[23] TQB[22] TQB[21] TQB[20] TQB[19] TQB[18] TQB[17] TQB[16]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the more significant word of the Transmit Queue Base address. The contents of the companion TMAC Transmit Descriptor Table Base LSW register is held in a holding register until a write access to this register, at which point, the base address of the transmit queue is updated.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TQB[31:0]: The transmit queue base bits (TQB[31:0]) provides the base address of the Transmit Descriptor Reference Free and Transmit Descriptor Reference Ready queue in PCI host memory. This register is initialised by the host. To calculate the physical address of a particular transmit queue element, the TQB bits are added with the appropriate queue start, end, read or write index registers to form the physical address. The base address must be dword aligned and thus the least significant two bits must be written to logic zero.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
204
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x318 : TMAC Descriptor Reference Free Queue Start Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TDRFQS[15] TDRFQS[14] TDRFQS[13] TDRFQS[12] TDRFQS[11] TDRFQS[10] TDRFQS[9] TDRFQS[8] TDRFQS[7] TDRFQS[6] TDRFQS[5] TDRFQS[4] TDRFQS[3] TDRFQS[2] TDRFQS[1] TDRFQS[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Transmit Descriptor Reference Free Queue start address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TDRFQS[15:0]: The transmit packet descriptor reference (TDR) free queue start bits (TDRFQS[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Free Queue start address. This register is initialised by the host. The physical start address of the TDRF queue is the sum of TDRFQS[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register.
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206
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x31C TMAC Descriptor Reference Free Queue Write Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TDRFQW[15] TDRFQW[14] TDRFQW[13] TDRFQW[12] TDRFQW[11] TDRFQW[10] TDRFQW[9] TDRFQW[8] TDRFQW[7] TDRFQW[6] TDRFQW[5] TDRFQW[4] TDRFQW[3] TDRFQW[2] TDRFQW[1] TDRFQW[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Transmit Descriptor Reference Free Queue write address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart.
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207
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TDRFQW[15:0]: The transmit packet descriptor reference (TPDR) free queue write bits (TDRFQW[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Free Queue write pointer. This register is initialised by the host. The physical write address in the TDRF queue is the sum of TDRFQW[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x320 : TMAC Descriptor Reference Free Queue Read Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TDRFQR[15] TDRFQR[14] TDRFQR[13] TDRFQR[12] TDRFQR[11] TDRFQR[10] TDRFQR[9] TDRFQR[8] TDRFQR[7] TDRFQR[6] TDRFQR[5] TDRFQR[4] TDRFQR[3] TDRFQR[2] TDRFQR[1] TDRFQR[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Transmit Descriptor Reference Free Queue read address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart.
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209
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TDRFQR[15:0]: The transmit packet descriptor reference (TPDR) free queue read bits (TDRFQR[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Free Queue read pointer. This register is initialised by the host. The physical read address in the TDRF queue is the sum of TDRFQR[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
210
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x324 : TMAC Descriptor Reference Free Queue End Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TDRFQE[15] TDRFQE[14] TDRFQE[13] TDRFQE[12] TDRFQE[11] TDRFQE[10] TDRFQE[9] TDRFQE[8] TDRFQE[7] TDRFQE[6] TDRFQE[5] TDRFQE[4] TDRFQE[3] TDRFQE[2] TDRFQE[1] TDRFQE[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Transmit Descriptor Reference Free Queue end address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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211
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TDRFQE[15:0]: The transmit packet descriptor reference (TDR) free queue end bits (TDRFQE[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Free Queue end address. This register is initialised by the host. The physical end address of the TDRF queue is the sum of TDRFQE[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register.
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212
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x328 :TMAC Descriptor Reference Ready Queue Start Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TDRRQS[15] TDRRQS[14] TDRRQS[13] TDRRQS[12] TDRRQS[11] TDRRQS[10] TDRRQS[9] TDRRQS[8] TDRRQS[7] TDRRQS[6] TDRRQS[5] TDRRQS[4] TDRRQS[3] TDRRQS[2] TDRRQS[1] TDRRQS[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Transmit Descriptor Reference Ready Queue start address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TDRRQS[15:0]: The transmit packet descriptor reference (TDR) ready queue start bits (TDRRQS[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Ready Queue start address. This register is initialised by the host. The physical start address of the TDRF queue is the sum of TDRRQS[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register.
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214
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x32C : TMAC Descriptor Reference Ready Queue Write Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TDRRQW[15] TDRRQW[14] TDRRQW[13] TDRRQW[12] TDRRQW[11] TDRRQW[10] TDRRQW[9] TDRRQW[8] TDRRQW[7] TDRRQW[6] TDRRQW[5] TDRRQW[4] TDRRQW[3] TDRRQW[2] TDRRQW[1] TDRRQW[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Transmit Descriptor Reference Ready Queue write address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TDRRQW[15:0]: The transmit packet descriptor reference (TPDR) ready queue write bits (TDRRQW[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Ready Queue write pointer. This register is initialised by the host. The physical write address in the TDRF queue is the sum of TDRRQW[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register.
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216
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x330 : TMAC Descriptor Reference Ready Queue Read Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TDRRQR[15] TDRRQR[14] TDRRQR[13] TDRRQR[12] TDRRQR[11] TDRRQR[10] TDRRQR[9] TDRRQR[8] TDRRQR[7] TDRRQR[6] TDRRQR[5] TDRRQR[4] TDRRQR[3] TDRRQR[2] TDRRQR[1] TDRRQR[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Transmit Descriptor Reference Ready Queue read address.
Notes
1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart.
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217
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TDRRQR[15:0]: The transmit packet descriptor reference (TPDR) ready queue read bits (TDRRQR[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Ready Queue read pointer. This register is initialised by the host. The physical read address in the TDRF queue is the sum of TDRRQR[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register.
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218
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x334 : TMAC Descriptor Reference Ready Queue End Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TDRRQE[15] TDRRQE[14] TDRRQE[13] TDRRQE[12] TDRRQE[11] TDRRQE[10] TDRRQE[9] TDRRQE[8] TDRRQE[7] TDRRQE[6] TDRRQE[5] TDRRQE[4] TDRRQE[3] TDRRQE[2] TDRRQE[1] TDRRQE[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register provides the Transmit Descriptor Reference Ready Queue end address.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TDRRQE[15:0]: The transmit packet descriptor reference (TDR) ready queue end bits (TDRRQE[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Ready Queue end address. This register is initialised by the host. The physical end address of the TDRF queue is the sum of TDRRQE[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register.
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220
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x380 : THDL Indirect Channel Select Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 to Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W
Type
Function
Unused
Default
XXXXH
BUSY CRWB Unused
X 0 XH
CHAN[9] CHAN[8] CHAN[7] CHAN[6] CHAN[5] CHAN[4] CHAN[3] CHAN[2] CHAN[1] CHAN[0]
0 0 0 0 0 0 0 0 0 0
This register provides the channel number used to access the transmit channel provision RAM. Writing to this register triggers an indirect channel register access.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. CHAN[9:0]: The indirect channel number bits (CHAN[9:0]) indicate the channel to be configured or interrogated in the indirect access.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
CRWB: The channel indirect access control bit (CRWB) selects between a configure (write) or interrogate (read) access to the channel provision RAM. Writing a logic zero to CRWB triggers an indirect write operation. Data to be written is taken from the Indirect Channel Data registers. Writing a logic one to CRWB triggers an indirect read operation. The data read can be found in the Indirect Channel Data registers. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the THDL Indirect Channel Data #1, #2 and #3 registers or to determine when a new indirect write operation may commence.
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222
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x384 : THDL Indirect Channel Data #1 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W W W W W W W W W W W W W
Type
Function
Unused
Default
XXXXH
PROV CRC[1] CRC[0] DELIN Reserved FPTR[10] FPTR[9] FPTR[8] FPTR[7] FPTR[6] FPTR[5] FPTR[4] FPTR[3] FPTR[2] FPTR[1] FPTR[0]
0 0 0 0 X 0 0 0 0 0 0 0 0 0 0 0
This register contains data read from the channel provision RAM after an indirect channel read operation or data to be inserted into the channel provision RAM in an indirect channel write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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223
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
FPTR[10:0]: The indirect FIFO block pointer (FPTR[10:0]) informs the partial packet buffer processor the circular linked list of blocks to use for a FIFO for the channel. The FIFO pointer to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. The FIFO pointer value can be any one of the block numbers provisioned, by indirect block write operations, to form the circular buffer. Reserved: The reserved bit must be set low for correct operation of the FREEDM84P672 device. DELIN: The indirect delineate enable bit (DELIN) configures the HDLC processor to perform flag sequence insertion and bit stuffing on the outgoing data stream. The delineate enable bit to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When DELIN is set high, flag sequence insertion, bit stuffing and ,optionally, CRC generation is performed on the outgoing HDLC data stream. When DELIN is set low, the HDLC processor does not perform any processing (flag sequence insertion, bit stuffing nor CRC generation) on the outgoing stream. DELIN reflects the value written until the completion of a subsequent indirect channel read operation. CRC[1:0]: The CRC algorithm (CRC[1:0]) configures the HDLC processor to perform CRC generation on the outgoing HDLC data stream. The value of CRC[1:0] to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. CRC[1:0] is ignored when DELIN is low. CRC[1:0] reflects the value written until the completion of a subsequent indirect channel read operation.
Table 32 - CRC[1:0] Settings CRC[1]
0 0 1 1
CRC[0]
0 1 0 1
Operation
No CRC CRC-CCITT CRC-32 Reserved
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224
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the channel provision RAM after an indirect channel read operation has completed. The provision enable flag to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the HDLC processor will service requests for data from the TCAS672 block. When PROV is set low, the HDLC processor will ignore requests from the TCAS672 block. PROV reflects the value written until the completion of a subsequent indirect channel read operation.
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225
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x388 : THDL Indirect Channel Data #2 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W W W W W W W W W W W W W
Type
Function
Unused
Default
XXXXH
7BIT PRIORITYB INVERT DFCS Reserved FLEN[10] FLEN[9] FLEN[8] FLEN[7] FLEN[6] FLEN[5] FLEN[4] FLEN[3] FLEN[2] FLEN[1] FLEN[0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This register contains data to be inserted into the channel provision RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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226
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
FLEN[10:0]: The indirect FIFO length (FLEN[10:0]) is the number of blocks, less one, that is provisioned to the circular channel FIFO specified by the FPTR[10:0] block pointer. The FIFO length to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. Reserved: The reserved bit must be set low for correct operation of the FREEDM84P672 device. DFCS: The diagnose frame check sequence bit (DFCS) controls the inversion of the FCS field inserted into the transmit packet. The value of DFCS to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When DFCS is set to one, the FCS field in the outgoing HDLC stream is logically inverted allowing diagnosis of downstream FCS verification logic. The outgoing FCS field is not inverted when DFCS is set to zero. DFCS reflects the value written until the completion of a subsequent indirect channel read operation. INVERT: The HDLC data inversion bit (INVERT) configures the HDLC processor to logically invert the outgoing HDLC stream. The value of INVERT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When INVERT is set to one, the outgoing HDLC stream is logically inverted. The outgoing HDLC stream is not inverted when INVERT is set to zero. INVERT reflects the value written until the completion of a subsequent indirect channel read operation. PRIORITYB: The active low channel FIFO starving enable bit (PRIORITYB) informs the partial packet processor of the priority of the channel relative to other channels when requesting data from the DMA port. The value of PRIORITYB to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. Channel FIFOs with PRIORITYB set to one are inhibited from making expedited requests for data to the TMAC672. When PRIORITYB is set to zero, both normal and expedited requests can be made to the TMAC672. Channels with HDLC data rate to FIFO size ratio that is significantly lower than other channels should have PRIORITYB set to one. PRIORITYB reflects the value written until the completion of a subsequent indirect channel read operation.
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227
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
7BIT: The least significant stuff enable bit (7BIT) configures the HDLC processor to stuff the least significant bit of each octet in the outgoing channel stream. The value of 7BIT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When 7BIT is set high, the least significant bit (last bit of each octet transmitted) does not contain channel data and is forced to the value configured by the BIT8 register bit. When 7BIT is set low, the entire octet contains valid data and BIT8 is ignored. 7BIT reflects the value written until the completion of a subsequent indirect channel read operation.
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228
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x38C : THDL Indirect Channel Data #3 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
TRANS IDLE Unused Unused LEVEL[3] LEVEL[2] LEVEL[1] LEVEL[0] FLAG[2] FLAG[1] FLAG[0] Unused XFER[3] XFER[2] XFER[1] XFER[0]
0 0 X X 0 0 0 0 0 0 0 X 0 0 0 0
This register contains data read from the channel provision RAM after an indirect read operation or data to be inserted into the channel provision RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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229
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
XFER[3:0]: The indirect channel transfer size (XFER[3:0]) specifies the amount of data the partial packet processor requests from the TMAC672 block. The channel transfer size to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When the channel FIFO free space reaches or exceeds the limit specified by XFER[3:0], the partial packet processor will make a request for data to the TMAC672 to retrieve the XFER[3:0] + 1 blocks of data. FIFO free space and transfer size are measured in the number of 16-byte blocks. XFER[3:0] reflects the value written until the completion of a subsequent indirect channel read operation. To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to be less than or equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the channel transfer size can be set, such that, the total number of blocks in the logical channel FIFO minus the start transmission level is an integer multiple of the channel transfer size. The case of a single block transfer size is a special. When BURSTEN is set high and XFER[3:0] = 'b0000, the transfer size is variable. The THDL672 will request the TMAC672 to transfer as much data as there is free space in the FIFO, up to a maximum set by BURST[3:0]. FLAG[2:0]: The flag insertion control (FLAG[2:0]) configures the minimum number of flags or bytes of idle bits the HDLC processor inserts between HDLC packets. The value of FLAG[2:0] to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. The minimum number of flags or bytes of idle (8 bits of 1's) inserted between HDLC packets is shown in the table below. FLAG[2:0] reflects the value written until the completion of a subsequent indirect channel read operation.
Table 33 - FLAG[2:0] Settings FLAG[2:0]
000 001 010 011 100
Minimum Number of Flag/Idle Bytes
1 flag / 0 Idle byte 2 flags / 0 idle byte 4 flags / 2 idle bytes 8 flags / 6 idle bytes 16 flags / 14 idle bytes
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230
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
FLAG[2:0]
101 110 111 LEVEL[3:0]:
Minimum Number of Flag/Idle Bytes
32 flags / 30 idle bytes 64 flags / 62 idle bytes 128 flags / 126 idle bytes
The indirect channel FIFO trigger level (LEVEL[3:0]), in concert with the TRANS bit, configure the various channel FIFO free space levels which trigger the HDLC processor to start transmission of a HDLC packet as well as trigger the partial packet buffer to make DMA request for data as shown in the following table. The channel FIFO trigger level to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. LEVEL[3:0] reflects the value written until the completion of a subsequent indirect channel read operation. The HDLC processor starts transmitting a packet when the channel FIFO free space is less than or equal to the level specified in the appropriate Start Transmission Level column of the following table or when an end of a packet is stored in the channel FIFO. When the channel FIFO free space is greater than or equal to the level specified in the Starving Trigger Level column of the following table and the HDLC processor is transmitting a packet and an end of a packet is not stored in the channel FIFO, the partial packet buffer makes expedite requests to the TMAC672 to retrieve XFER[3:0] + 1 blocks of data. To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to be less than or equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the channel transfer size can be set such that the total number of blocks in the logical channel FIFO, minus the start transmission level, is an integer multiple of the channel transfer size. The starving trigger level must always be set to a number of blocks greater than or equal to the channel transfer size. IDLE: The interframe time fill bit (IDLE) configures the HDLC processor to use flag bytes or HDLC idle as the interframe time fill between HDLC packets. The value of IDLE to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When IDLE is set low, the HDLC processor uses flag bytes as the interframe time fill. When IDLE is set high, the HDLC processor uses HDLC idle (all one's bit with no bit-stuffing pattern is transmitted) as the interframe time fill. IDLE reflects the value written until the completion of a subsequent indirect channel read operation.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TRANS: The indirect transmission start bit (TRANS), in concert with the LEVEL[3:0] bits, configure the various channel FIFO free space levels which trigger the HDLC processor to start transmission of a HDLC packet as well as trigger the partial packet buffer to make DMA request for data as shown in the following table. The transmission start mode to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. TRANS reflects the value written until the completion of a subsequent indirect channel read operation. The HDLC processor starts transmitting a packet when the channel FIFO free space is less than or equal to the level specified in the appropriate Start Transmission Level column of the following table or when an end of a packet is stored in the channel FIFO. When the channel FIFO free space is greater than or equal to the level specified in the Starving Trigger Level column of the following table and the HDLC processor is transmitting a packet and an end of a packet is not stored in the channel FIFO, the partial packet buffer makes expedite requests to the TMAC672 to retrieve XFER[3:0] + 1 blocks of data. To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to be less than or equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the channel transfer size can be set, such that, the total number of blocks in the logical channel FIFO minus the start transmission level is an integer multiple of the channel transfer size. The starving trigger level must always be set to a number of blocks greater than or equal to the channel transfer size.
Table 34 - Level[3:0]/TRANS Settings LEVEL[3:0] Starving Trigger Level
2 Blocks (32 bytes free) 3 Blocks (48 bytes free) 4 Blocks (64 bytes free) 6 Blocks (96 bytes free) 8 Blocks (128 bytes free)
Start Transmission Level (TRANS=0)
1 Block (16 bytes free) 2 Blocks (32 bytes free) 3 Blocks (48 bytes free) 4 Blocks (64 bytes free) 6 Blocks (96 bytes free)
Start Transmission Level (TRANS=1)
1 Block (16 bytes free) 1 Block (16 bytes free) 2 Blocks (32 bytes free) 3 Blocks (48 bytes free) 4 Blocks (64 bytes free)
232
0000 0001 0010 0011 0100
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
LEVEL[3:0]
Starving Trigger Level
12 Blocks (192 bytes free) 16 Blocks (256 bytes free) 24 Blocks (384 bytes free) 32 Blocks (512 bytes free) 48 Blocks (768 bytes free) 64 Blocks (1 Kbytes free) 96 Blocks (1.5 Kbytes free) 192 Blocks (3 Kbytes free) 384 Blocks (6 Kbytes free) 768 Blocks (12 Kbytes free) 1536 Blocks (24 Kbytes free)
Start Transmission Level (TRANS=0)
8 Blocks (128 bytes free) 12 Blocks (192 bytes free) 16 Blocks (256 bytes free) 24 Blocks (384 bytes free) 32 Blocks (512 bytes free) 48 Blocks (768 bytes free) 64 Blocks (1 Kbytes free) 128 Blocks (2 Kbytes free) 256 Blocks (4 Kbytes free) 512 Blocks (8 Kbytes free) 1024 Blocks (16 Kbytes free)
Start Transmission Level (TRANS=1)
6 Blocks (96 bytes free) 8 Blocks (128 bytes free) 12 Blocks (192 bytes free) 16 Blocks (256 bytes free) 24 Blocks (384 bytes free) 32 Blocks (512 bytes free) 48 Blocks (768 bytes free) 96 Blocks (1.5 Kbytes free) 192 Blocks (2 Kbytes free) 384 Blocks (4 Kbytes free) 768 Blocks (8 Kbytes free)
0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
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233
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x3A0 : THDL Indirect Block Select Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 to Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W
Type
Function
Unused
Default
XXXXH
BUSY BRWB Unused
X 0 XH
Reserved BLOCK[10] BLOCK[9] BLOCK[8] BLOCK[7] BLOCK[6] BLOCK[5] BLOCK[4] BLOCK[3] BLOCK[2] BLOCK[1] BLOCK[0]
X 0 0 0 0 0 0 0 0 0 0 0
This register provides the block number used to access the block pointer RAM. Writing to this register triggers an indirect block register access.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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234
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
BLOCK[10:0]: The indirect block number (BLOCK[10:0]) indicate the block to be configured or interrogated in the indirect access. Reserved: The reserved bit must be set low for correct operation of the FREEDM84P672 device. BRWB: The block indirect access control bit (BRWB) selects between a configure (write) or interrogate (read) access to the block pointer RAM. Writing a logic zero to BRWB triggers an indirect block write operation. Data to be written is taken from the Indirect Block Data register. Writing a logic one to BRWB triggers an indirect block read operation. The data read can be found in the Indirect Block Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the THDL Indirect Block Data register or to determine when a new indirect write operation may commence.
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235
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x3A4 : THDL Indirect Block Data Bit
Bit 31 to Bit 16 Bit 15 Bit 14 to Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
Reserved Unused
0 XH
Reserved BPTR[10] BPTR[9] BPTR[8] BPTR[7] BPTR[6] BPTR[5] BPTR[4] BPTR[3] BPTR[2] BPTR[1] BPTR[0]
X 0 0 0 0 0 0 0 0 0 0 0
This register contains data read from the transmit block pointer RAM after an indirect block read operation or data to be inserted into the transmit block pointer RAM in an indirect block write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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236
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
BPTR[10:0]: The indirect block pointer (BPTR[10:0]) configures the block pointer of the block specified by the Indirect Block Select register. The block pointer to be written to the transmit block pointer RAM, in an indirect write operation, must be set up in this register before triggering the write. The block pointer value is the block number of the next block in the linked list. A circular list of blocks must be formed in order to use the block list as a channel FIFO buffer. FPTR[10:0] reflects the value written until the completion of a subsequent indirect block read operation. When provisioning a channel FIFO, all blocks pointers must be re-written to properly initialize the FIFO. Reserved: The reserved bits must be set low for correct operation of the FREEDM84P672 device.
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237
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x3B0 : THDL Configuration Bit
Bit 31 to Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXH
BIT8 TSTD BURSTEN Unused Unused Unused BURST[3] BURST[2] BURST[1] BURST[0]
0 0 0 X X X 0 0 0 0
This register configures all provisioned channels.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. BURST[3:0]: The DMA burst length bits (BURST[3:0]) configure the maximum amount of transmit data that can be requested in a single DMA transaction for channels whose channel transfer size is set to one block (XFER[3:0] = 'b0000). BURST[3:0] has no effect when BURSTEN is set low, nor on channels configured with other transfer sizes. BURST[3:0] defines the maximum number of 16 byte blocks, less one, that is transferred in each DMA transaction. Thus, the minimum number of blocks is one (16 bytes) and the maximum is sixteen (256 bytes).
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238
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
BURSTEN: The burst length enable bit (BURSTEN) controls the use of BURST[3:0] in determining the amount of data requested in a single DMA transaction for channels whose channel transfer size is set to one block (XFER[3:0] = 'b0000). BURSTEN has no effect on channels configured with other transfer sizes. When BURSTEN is set high, the maximum size of DMA transfer is limited by BURST[3:0]. The transmit HDLC processor may combine several channel transfer size amounts into a single transaction. When BURSTEN is set low, the amount of data in a DMA transfer is limited to one block. TSTD: The telecom standard bit (TSTD) controls the bit ordering of the HDLC data transferred from the PCI host. When TSTD is set low, the least significant bit of the each byte on the PCI bus (AD[0], AD[8], AD[16] and AD[24]) is the first HDLC bit transmitted and the most significant bit of each byte (AD[7], AD[15], AD[23] and AD[31]) is the last HDLC bit transmitted (datacom standard). When TSTD is set high, AD[0], AD[8], AD[16] and AD[24] are the last HDLC bit transmitted and AD[7], AD[15], AD[23] and AD[31] are the first HDLC bit transmitted (telecom standard). BIT8: The least significant stuff control bit (BIT8) carries the value placed in the least significant bit of each octet when the HDLC processor is configured (7BIT set high) to stuff the least significant bit of each octet in the corresponding transmit link (TD[n]). When BIT8 is set high, the least significant bit (last bit of each octet transmitted) is forced high. When BIT8 is set low, the least significant bit is forced low. BIT8 is ignored when 7BIT is set low.
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239
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x400 : TCAS Indirect Link and Time-slot Select Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W
Type
Function
Unused
Default
XXXXH
BUSY RWB Unused LINK[6] LINK[5] LINK[4] LINK[3] LINK[2] LINK[1] LINK[0] Unused TSLOT[4] TSLOT[3] TSLOT[2] TSLOT[1] TSLOT[0]
X 0 X 0 0 0 0 0 0 0 X 0 0 0 0 0
This register provides the link number and time-slot number used to access the transmit channel provision RAM. Writing to this register triggers an indirect register access and transfers the contents of the Indirect Channel Data register to an internal holding register.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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240
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
TSLOT[4:0]: The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be configured or interrogated in the indirect access. For a channelised T1/J1 link, time-slots 1 to 24 are valid. For a channelised E1 link, time-slots 1 to 31 are valid. For unchannelised or unframed links, only time-slot 0 is valid. LINK[6:0]: The indirect link number bits (LINK[6:0]) select amongst the 84 transmit links to be configured or interrogated in the indirect access. RWB: The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the transmit channel provision RAM. The address to the transmit channel provision RAM is constructed by concatenating the TSLOT[4:0] and LINK[4:0] bits. Writing a logic zero to RWB triggers an indirect write operation. Data to be written is taken from the PROV and the CHAN[9:0] bits of the Indirect Data register. Writing a logic one to RWB triggers an indirect read operation. Addressing of the RAM is the same as in an indirect write operation. The data read can be found in the PROV and the CHAN[9:0] bits of the Indirect Channel Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the TCAS Indirect Channel Data register or to determine when a new indirect write operation may commence.
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241
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x404 : TCAS Indirect Channel Data Bit
Bit 31 to Bit 16 Bit 15 Bit 14 to Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
PROV Unused
0 XXH
CHAN[9] CHAN[8] CHAN[7] CHAN[6] CHAN[5] CHAN[4] CHAN[3] CHAN[2] CHAN[1] CHAN[0]
0 0 0 0 0 0 0 0 0 0
This register contains the data read from the transmit channel provision RAM after an indirect read operation or the data to be inserted into the transmit channel provision RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. CHAN[9:0]: The indirect data bits (CHAN[9:0]) report the channel number read from the transmit channel provision RAM after an indirect read operation has completed. Channel number to be written to the transmit channel provision RAM in an indirect write operation must be set up in this register before
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
triggering the write. CHAN[9:0] reflects the value written until the completion of a subsequent indirect read operation. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from transmit channel provision RAM after an indirect read operation has completed. The provision enable flag to be written to the transmit channel provision RAM in an indirect write operation must be set up in this register before triggering the write. When PROV is set high, the current time-slot is assigned to the channel as indicated by CHAN[9:0]. When PROV is set low, the time-slot does not belong to any channel. The transmit link data is set to the contents of the Idle Time-slot Fill Data register. PROV reflects the value written until the completion of a subsequent indirect read operation.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x40C : TCAS Idle Time-slot Fill Data Bit
Bit 31 to Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXH
FDATA[7] FDATA[6] FDATA[5] FDATA[4] FDATA[3] FDATA[2] FDATA[1] FDATA[0]
1 1 1 1 1 1 1 1
This register contains the data to be written to disabled time-slots of a channelised link.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. FDATA[7:0]: The fill data bits (FDATA[7:0]) are transmitted during disabled (PROV set low) time-slots of channelised links.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x410 : TCAS Channel Disable Bit
Bit 31 to Bit 16 Bit 15 Bit 14 to Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
CHDIS Unused
0 XXH
DCHAN[9] DCHAN[8] DCHAN[7] DCHAN[6] DCHAN[5] DCHAN[4] DCHAN[3] DCHAN[2] DCHAN[1] DCHAN[0]
0 0 0 0 0 0 0 0 0 0
This register controls the disabling of one specific channel to allow orderly provisioning of time-slots.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. DCHAN[9:0]: The disable channel number bits (DCHAN[9:0]) selects the channel to be disabled. When CHDIS is set high, the channel specified by DCHAN[9:0] is disabled. Data in time-slots associated with the specified channel is set to FDATA[7:0] in the Idle Time-slot Fill Data register. When CHDIS is set low, the channel specified by DCHAN[9:0] operates normally.
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
CHDIS: The channel disable bit (CHDIS) controls the disabling of the channels specified by DCHAN[9:0]. When CHDIS is set high, the channel selected by DCHAN[9:0] is disabled. Data in time-slots associated with the specified channel is set to FDATA[7:0] in the Idle Time-slot Fill Data register. When CHDIS is set low, the channel specified by DCHAN[9:0] operates normally.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x440 : TCAS SBI SPE1 Configuration Register #1 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
FEN[11] FEN[10] FEN[9] FEN[8] FEN[7] FEN[6] FEN[5] FEN[4] FEN[3] FEN[2] FEN[1] FEN[0] Unused SBI_MODE[2] SBI_MODE[1] SBI_MODE[0]
0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0
This register configures the operational mode of transmit links 0, 3, 6, 9, ... 33, 36, 39, ...81, i.e. those links mapped to SPE 1 of the SBI ADD BUS.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SBI_MODE[2:0]: The SBI mode select bits (SBI_MODE[2:0]) configure the transmit links of SPE1, as shown in the following table:
Table 35 - SBI Mode SPE1 Configuration SBI_MODE [2:0] 000 001 010 011 100 101 110 111
FEN[11:0] Each FEN bit, FEN[n], configures link 3n for framed operation. In unframed operation (FEN[n] = 0), HDLC data is transmitted in all framing bit locations. In framed mode (FEN[n] = 1), the framing bit locations are unused.
SPE1 Configuration Single unchannelised DS-3 on link 0 28 T1/J1 links 21 E1 links (links 63, 66, 69, ... , 81 are unused) Reserved Reserved Reserved Reserved Reserved
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x444 : TCAS SBI SPE1 Configuration Register #2 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
FEN[27] FEN[26] FEN[25] FEN[24] FEN[23] FEN[22] FEN[21] FEN[20] FEN[19] FEN[18] FEN[17] FEN[16] FEN[15] FEN[14] FEN[13] FEN[12]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The bits of this register set are used to configure the framing modes of transmit links 36, 39, 42 ... 81.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
FEN[27:12]: Each FEN bit, FEN[n], configures link 3n for framed operation. In unframed operation (FEN[n] = 0), HDLC data is transmitted in all framing bit locations. In framed mode (FEN[n] = 1), the framing bit locations are unused.
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250
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x448 : TCAS SBI SPE2 Configuration Register #1 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
FEN[11] FEN[10] FEN[9] FEN[8] FEN[7] FEN[6] FEN[5] FEN[4] FEN[3] FEN[2] FEN[1] FEN[0] Unused SBI_MODE[2] SBI_MODE[1] SBI_MODE[0]
0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0
This register configures the operational mode of transmit links 1, 4, 7, 10, ... 34, 37, ...82, i.e. those links mapped to SPE 2 of the SBI ADD BUS.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SBI_MODE[2:0]: The SBI mode select bits (SBI_MODE[2:0]) configure the transmit links of SPE2, as shown in the following table:
Table 36 - SBI Mode SPE2 Configuration SBI_MODE [2:0] 000 001 010 011 100 101 110 111
FEN[11:0] Each FEN bit, FEN[n], configures link 3n+1 for framed operation. In unframed operation (FEN[n] = 0), HDLC data is transmitted in all framing bit locations. In framed mode (FEN[n] = 1), the framing bit locations are unused.
SPE2 Configuration Single unchannelised DS-3 on link 1 28 T1/J1 links 21 E1 links (links 64, 67, 70, ... , 82 are unused) Reserved Reserved Reserved Reserved Reserved
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x44C : TCAS SBI SPE2 Configuration Register #2 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
FEN[27] FEN[26] FEN[25] FEN[24] FEN[23] FEN[22] FEN[21] FEN[20] FEN[19] FEN[18] FEN[17] FEN[16] FEN[15] FEN[14] FEN[13] FEN[12]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The bits of this register set are used to configure the framing modes of transmit links 37, 40, 43 ... 82.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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253
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
FEN[27:12]: Each FEN bit, FEN[n], configures link 3n+1 for framed operation. In unframed operation (FEN[n] = 0), HDLC data is transmitted in all framing bit locations. In framed mode (FEN[n] = 1), the framing bit locations are unused.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
254
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x450 : TCAS SBI SPE3 Configuration Register #1 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
FEN[11] FEN[10] FEN[9] FEN[8] FEN[7] FEN[6] FEN[5] FEN[4] FEN[3] FEN[2] FEN[1] FEN[0] Unused SBI_MODE[2] SBI_MODE[1] SBI_MODE[0]
0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0
This register configures the operational mode of transmit links 2, 5, 8, 11, ... 35, 38, ...83, i.e. those links mapped to SPE 3 of the SBI ADD BUS.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
SBI_MODE[2:0]: The SBI mode select bits (SBI_MODE[2:0]) configure the transmit links of SPE3, as shown in the following table:
Table 37 - SBI Mode SPE3 Configuration SBI_MODE [2:0] 000 001 010 011 100 101 110 111
FEN[11:0] Each FEN bit, FEN[n], configures link 3n+2 for framed operation. In unframed operation (FEN[n] = 0), HDLC data is transmitted in all framing bit locations. In framed mode (FEN[n] = 1), the framing bit locations are unused.
SPE3 Configuration Single unchannelised DS-3 on link 2 28 T1/J1 links 21 E1 links (links 65, 68, 71, ... , 83 are unused) Reserved Reserved Reserved Reserved Reserved
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x454 : TCAS SBI SPE3 Configuration Register #2 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXH
FEN[27] FEN[26] FEN[25] FEN[24] FEN[23] FEN[22] FEN[21] FEN[20] FEN[19] FEN[18] FEN[17] FEN[16] FEN[15] FEN[14] FEN[13] FEN[12]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The bits of this register set are used to configure the framing modes of transmit links 38, 41, 44 ... 83.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
FEN[27:12]: Each FEN bit, FEN[n], configures link 3n+2 for framed operation. In unframed operation (FEN[n] = 0), HDLC data is transmitted in all framing bit locations. In framed mode (FEN[n] = 1), the framing bit locations are unused.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
258
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x480 - 0x488 : TCAS Links #0 to #2 Configuration Bit
Bit 31 to Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXXH
Reserved Unused Reserved Reserved Reserved
0 X 0 0 0
This register controls the operation of transmit links #0 to #2 when they are configured to transmit data on the TD[2:0] outputs (i.e. SPEn_EN is low).
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. Reserved: The reserved bits must be set low for correct operation of the FREEDM84P672 device.
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259
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x500 : PMON Status Bit
Bit 31 to Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R
Type
Function
Unused
Default
XXXXXXXH
C2DET C1DET UFDET OFDET Unused Unused
X X X X X X
This register contains status information indicating whether a non-zero count has been latched in the count registers.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. OFDET: The overflow detect bit (OFDET) indicates the status of the PMON Receive FIFO Overflow Count register. OFDET is set high when overflow events have occurred during the latest PMON accumulation interval. OFDET is set low if no overflow events are detected. UFDET: The underflow detect bit (UFDET) indicates the status of the PMON Transmit FIFO Underflow Count register. UFDET is set high when underflow events have occurred during the latest PMON accumulation interval. UFDET is set low if no underflow events are detected. C1DET: The configurable event #1 detect bit (C1DET) indicates the status of the PMON Configurable Count #1 register. C1DET is set high when selected
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PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
events have occurred during the latest PMON accumulation interval. C1DET is set low if no selected events are detected. C2DET: The configurable event #2 detect bit (C2DET) indicates the status of the PMON Configurable Count #2 register. C2DET is set high when selected events have occurred during the latest PMON accumulation interval. C2DET is set low if no selected events are detected.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
261
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x504 : PMON Receive FIFO Overflow Count Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R R R R R R R R R R
Type
Function
Unused
Default
XXXXH
OF[15] OF[14] OF[13] OF[12] OF[11] OF[10] OF[9] OF[8] OF[7] OF[6] OF[5] OF[4] OF[3] OF[2] OF[1] OF[0]
X X X X X X X X X X X X X X X X
This register reports the number of receive FIFO overflow events in the previous accumulation interval.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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262
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
OF[15:0]: The OF[15:0] bits reports the number of receive FIFO overflow events that have been detected since the last time this register was polled. This register is polled by writing to the FREEDM-84P672 Master Clock / Frame Pulse Activity Monitor and Accumulation Trigger register. The write access transfers the internally accumulated error count to the FIFO overflow register and simultaneously resets the internal counter to begin a new cycle of error accumulation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
263
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x508 : PMON Transmit FIFO Underflow Count Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R R R R R R R R R R
Type
Function
Unused
Default
XXXXH
UF[15] UF[14] UF[13] UF[12] UF[11] UF[10] UF[9] UF[8] UF[7] UF[6] UF[5] UF[4] UF[3] UF[2] UF[1] UF[0]
X X X X X X X X X X X X X X X X
This register reports the number of transmit FIFO underflow events in the previous accumulation interval.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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264
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
UF[15:0]: The UF[15:0] bits reports the number of transmit FIFO underflow events that have been detected since the last time this register was polled. This register is polled by writing to the FREEDM-84P672 Master Clock / Frame Pulse Activity Monitor and Accumulation Trigger register. The write access transfers the internally accumulated error count to the FIFO underflow register and simultaneously resets the internal counter to begin a new cycle of error accumulation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
265
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x50C : PMON Configurable Count #1 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R R R R R R R R R R
Type
Function
Unused
Default
XXXXH
C1[15] C1[14] C1[13] C1[12] C1[11] C1[10] C1[9] C1[8] C1[7] C1[6] C1[5] C1[4] C1[3] C1[2] C1[1] C1[0]
X X X X X X X X X X X X X X X X
This register reports the number events, selected by the FREEDM-84P672 Master Performance Monitor Control register, that occurred in the previous accumulation interval.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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266
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
C1[15:0]: The C1[15:0] bits reports the number of selected events that have been detected since the last time this register was polled. This register is polled by writing to the FREEDM-84P672 Master Clock / Frame Pulse Activity Monitor and Accumulation Trigger register. The write access transfers the internally accumulated error count to the configurable count #1 register and simultaneously resets the internal counter to begin a new cycle of event accumulation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
267
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x510 : PMON Configurable Count #2 Bit
Bit 31 to Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R R R R R R R R R R
Type
Function
Unused
Default
XXXXH
C2[15] C2[14] C2[13] C2[12] C2[11] C2[10] C2[9] C2[8] C2[7] C2[6] C2[5] C2[4] C2[3] C2[2] C2[1] C2[0]
X X X X X X X X X X X X X X X X
This register reports the number events, selected by the FREEDM-84P672 Master Performance Monitor Control register, that occurred in the previous accumulation interval.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register.
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268
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
C2[15:0]: The C2[15:0] bits reports the number of selected events that have been detected since the last time this register was polled. This register is polled by writing to the FREEDM-84P672 Master Clock / Frame Pulse Activity Monitor and Accumulation Trigger register. The write access transfers the internally accumulated error count to the configurable count #2 register and simultaneously resets the internal counter to begin a new cycle of event accumulation.
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269
PM7384 FREEDM-84P672
DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Register 0x5C0 : SBI EXTRACT Control Bit
Bit 15 to Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXH
Reserved Unused Unused Reserved Reserved Reserved SBI_PERR_EN SBI_PAR_CTL
0 X X 0 0 0 0 1
This register controls the operation of the SBI EXTRACT block.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. SBI_PAR_CTL The SBI_PAR_CTL bit is used to configure the Parity mode for checking of the SBI parity signal, DDP as follows: When SBI_PAR_CTL is '0' parity is even. When SBI_PAR_CTL is `1' parity is odd. SBI_PERR_EN The SBI_PERR_EN bit is used to enable SBI Parity Error interrupt generation. When SBI_PERR_EN is `0', SBI Parity Error Interrupts are disabled. When SBI_PERR_EN is `1', SBI Parity Error Interrupts are enabled. In both cases the SBI Parity checker logic will update the SBI EXTRACT Parity Error Interrupt Reason Register when a parity error occurs.
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Reserved: The reserved bits must be set low for correct operation of the FREEDM84P672 device.
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Register 0x5CC : SBI EXTRACT Tributary RAM Indirect Access Address Bit
Bit 31 to Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXH
Reserved SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0]
0 0 0 0 0 0 0 0
This register provides the receive SPE and link number used to access the SBI EXTRACT tributary control configuration RAM.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. TRIB[4:0] and SPE[1:0] The TRIB[4:0] and SPE[1:0] fields are used to specify which SBI tributary the control configuration RAM write or read operation will apply to. Legal values for TRIB[4:0] are b'00001' through b`11100'. Legal values for SPE[1:0] are b'01' through b`11'. Reserved: The reserved bit must be set low for correct operation of the FREEDM84P672 device.
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Register 0x5D0 : SBI EXTRACT Tributary RAM Indirect Access Control Bit
Bit 31 to Bit 8 Bit 7 Bit 6 to Bit 2 Bit 1 Bit 0 R/W R/W R/W
Type
Function
Unused
Default
XXXXXXH
BUSY Unused
X XXH
RWB Reserved
0 0
This register controls access the SBI EXTRACT tributary control configuration RAM. Writing to this register triggers an indirect register access.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. Reserved: The reserved bit must be set low for correct operation of the FREEDM84P672 device. RWB The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the tributary control configuration RAM. Writing a `0' to RWB triggers an indirect write operation. Data to be written is taken from the SBI EXTRACT Tributary RAM Indirect Access Data Register. Writing a `1' to RWB triggers an indirect read operation. The data read can be found in the SBI EXTRACT Tributary RAM Indirect Access Data Register. BUSY The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when a write to the SBI EXTRACT Tributary RAM Indirect Access Control Register triggers an indirect access and will stay high until the access is complete. This register should be polled to determine
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when data from an indirect read operation is available in the SBI EXTRACT Tributary RAM Indirect Access Data Register or to determine when a new indirect write operation may commence.
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Register 0x5D8 : SBI EXTRACT Tributary RAM Indirect Access Data Bit
Bit 31 to Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXXH
Reserved Reserved Reserved TRIB_TYP[1] TRIB_TYP[0] Reserved ENBL
0 0 0 0 0 0 0
This register contains data read from the SBI EXTRACT tributary control configuration RAM after an indirect read operation or data to be written to the tributary control configuration RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. ENBL The ENBL bit is used to enable the Tributary. Writing to the SBI EXTRACT tributary control configuration RAM with the ENBL bit set enables the SBI EXTRACT block to take tributary data from an SBI tributary and output that data to the SBI PISO blocks. Reserved: The reserved bits must be set low for correct operation of the FREEDM84P672 device. TRIB_TYP[1:0] The TRIB_TYP[1:0] field is used to specify the characteristics of the SBI tributary as shown in Table 38 below:
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Table 38 - TRIB_TYP Encoding TRIB_TYP[1:0] 00 01 10 11 Tributary type Reserved Framed Unframed Reserved
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Register 0x5DC : SBI EXTRACT Parity Error Interrupt Reason Bit
Bit 31 to Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R
Type
Function
Unused
Default
XXXXXXH
SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0] PERRI
0 1 0 0 0 0 1 0
This register provides information about the most recent parity error on the SBI DROP BUS.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PERRI When set PERRI indicates that an SBI parity error has been detected. Reading the SBI EXTRACT Parity Error Interrupt Reason Register clears this bit. TRIB[4:0] and SPE[1:0] The TRIB[4:0] and SPE[1:0] fields specify the SBI tributary for which a parity error was detected. These fields are only valid when PERRI is set.
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Register 0x680 : SBI INSERT Control Bit
Bit 31 to Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXH
Reserved Unused Unused Reserved Reserved Reserved Unused SBI_PAR_CTL
0 X X 0 0 0 X 1
This register controls the operation of the SBI INSERT block.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. SBI_PAR_CTL The SBI_PAR_CTL bit is used to configure the Parity mode for generation of the SBI parity signal, ADP as follows: When SBI_PAR_CTL is '0' parity is even. When SBI_PAR_CTL is `1' parity is odd. Reserved: The reserved bits must be set low for correct operation of the FREEDM84P672 device.
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Register 0x68C : SBI INSERT Tributary RAM Indirect Access Address Bit
Bit 31 to Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXH
Reserved SPE[1] SPE[0] TRIB[4] TRIB[3] TRIB[2] TRIB[1] TRIB[0]
0 0 0 0 0 0 0 0
This register provides the transmit SPE and link number used to access the SBI INSERT tributary control configuration RAM.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. TRIB[4:0] and SPE[1:0] The TRIB[4:0] and SPE[1:0] fields are used to specify which SBI tributary the control configuration RAM write or read operation will apply to. Legal values for TRIB[4:0] are b'00001' through b`11100'. Legal values for SPE[1:0] are b'01' through b`11'. Reserved: The reserved bit must be set low for correct operation of the FREEDM84P672 device.
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Register 0x690 : SBI INSERT Tributary RAM Indirect Access Control Bit
Bit 31 to Bit 8 Bit 7 Bit 6 to Bit 2 Bit 1 Bit 0 R/W R/W R/W
Type
Function
Unused
Default
XXXXXXH
BUSY Unused
X XXH
RWB Reserved
0 0
This register controls access to the SBI INSERT tributary control configuration RAM. Writing to this register triggers an indirect register access.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. Reserved: The reserved bits must be set low for correct operation of the FREEDM84P672 device. RWB The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the tributary control configuration RAM. Writing a `0' to RWB triggers an indirect write operation. Data to be written is taken from the SBI INSERT Tributary RAM Indirect Access Data Register. Writing a `1' to RWB triggers an indirect read operation. The data read can be found in the SBI INSERT Tributary RAM Indirect Access Data Register. BUSY The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when a write to the SBI INSERT Tributary RAM Indirect Access Control Register triggers an indirect access and will stay high until the access is complete. This register should be polled to determine
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when data from an indirect read operation is available in the SBI INSERT Tributary RAM Indirect Access Data Register or to determine when a new indirect write operation may commence.
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Register 0x698 : SBI INSERT Tributary RAM Indirect Access Data Bit
Bit 31 to Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W
Type
Function
Unused
Default
XXXXXXXH
CLK_MSTR TRIB_TYP[1] TRIB_TYP[0] Reserved ENBL
0 0 0 0 0
This register contains data read from the SBI INSERT tributary control configuration RAM after an indirect read operation or data to be written to the tributary control configuration RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. ENBL The ENBL bit is used to enable the Tributary. Writing to the SBI INSERT tributary control configuration RAM with the ENBL bit set enables the SBI INSERT block to output tributary data on an SBI tributary. Reserved: The reserved bit must be set low for correct operation of the FREEDM84P672 device. TRIB_TYP[1:0] The TRIB_TYP[1:0] field is used to specify the characteristics of the SBI tributary as shown in Table 39 below:
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Table 39 - TRIB_TYP Encoding TRIB_TYP[1:0] 00 01 10 11
CLK_MSTR The CLK_MSTR bit configures the SBI tributary to operate as a timing master or slave. Setting CLK_MSTR to 1 configures the tributary as a timing master (AJUST_REQ input ignored). Setting CLK_MSTR to 0 configures the tributary as a timing slave (requests on AJUST_REQ honoured).
Tributary type Reserved Framed Unframed Reserved
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11
PCI CONFIGURATION REGISTER DESCRIPTION
PCI configuration registers are implemented by the PCI Interface. These registers can only be accessed when the PCI Interface is a target and a configuration cycle is in progress as indicated using the IDSEL input.
Notes on PCI Configuration Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. Except where noted, all configuration bits that can be written into can also be read back. This allows the processor controlling the FREEDM-84P672 to determine the programming state of the block. 3. Writable PCI configuration register bits are cleared to logic zero upon reset unless otherwise noted. 4. Writing into read-only PCI configuration register bit locations does not affect FREEDM-84P672 operation unless otherwise noted. 5. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the FREEDM84P672 operates as intended, reserved register bits must only be written with their default values. Similarly, writing to reserved registers should be avoided.
11.1 PCI Configuration Registers
PCI configuration registers can only be accessed by the PCI host. For each register description below, the hexadecimal register number indicates the PCI offset.
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Register 0x00 : Vendor Identification/Device Identification Bit
Bit 31 to Bit 16 Bit 15 to Bit 0 VNDRID[15:0]: The VNDRID[15:0] bits identifies the manufacturer of the device. Valid vendor identifiers are allocated by the PCI SIG. DEVID[15:0]: The DEVID[15:0] bits define the particular device. Valid device identifiers will be specified by PMC-Sierra. The default value of DEVID[15:0] is that of the FREEDM-84P672 device.
Type
R
Function
DEVID[15:0]
Default
7384H
R
VNDRID[15:0]
11F8H
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Register 0x04 : Command/Status Bit
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 to Bit 16 Bit 15 to Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type
R/W R/W R/W R/W R/W R R R/W R R R R
Function
PERR SERR MABT RTABT TABT DVSLT[1] DVSLT[0] DPR FBTBE Reserved 66MHZ_CAPABLE Reserved
Default
0 0 0 0 0 0 1 0 1 0 1 00H
R
Reserved
00H
R R/W R R/W R R R R/W R/W R
FBTBEN SERREN ADSTP PERREN VGASNP MWAI SPCEN MSTREN MCNTRL IOCNTRL
0 0 0 0 0 0 0 0 0 0
The lower 16 bits of this register make up the Command register which provides basic control over the GPIC's ability to respond to PCI accesses. When a 0 is
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written to all bits in the command register, the GPIC is logically disconnected from the PCI bus for all accesses except configuration accesses. The upper 16bits is used to record status information for PCI bus related events. Reads to the status portion of this register behave normally. Writes are slightly different in that bits can be reset, but not set. A bit is reset whenever the register is written, and the data in the corresponding bit location is a 1. IOCNTRL: When IOCNTRL is set to zero, the GPIC will not respond to PCI bus I/O accesses. MCNTRL: When MCNTRL is set to one, the GPIC will respond to PCI bus memory accesses. Clearing MCNTRL disables memory accesses. MSTREN: When MSTREN is set to one, the GPIC can act as a Master. Clearing MSTREN disables the GPIC from becoming a Master. SPCEN: The GPIC does not decode PCI special cycles. The SPCEN bit is forced low. MWAI: The GPIC does not generate memory-write-and-invalidate commands. The MWAI bit is forced low. VGASNP: The GPIC is not a VGA device. The VGASNP bit is forced low. PERREN: When the PERREN bit is set to one, the GPIC can report parity errors. Clearing the PERREN bit causes the GPIC to ignore parity errors. ADSTP: The GPIC does not perform address and data stepping. The ADSTP bit is forced low. SERREN: When the SERREN bit is set high, the GPIC can drive the SERRB line. Clearing the SERREN bit disables the SERRB line. SERREN and PERREN must be set to report an address parity error.
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FBTBEN: As a master, the GPIC does not generate fast back-to-back cycles to different devices. This bit is forced low. The upper 16-bits make up the PCI Status field. The status field tracks the status of PCI bus related events. Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set. A bit is reset whenever the register is written, and the data in the corresponding bit location is a one. 66MHZ_CAPABLE: The 66 MHz Capable bit is hardwired to one to indicate the GPIC is capable of operating in 66 MHz mode. FBTBE: The FBTBE bit is hardwired to one to indicate the GPIC supports fast backto-back transactions with other targets. DPR: The Data Parity Reported (DPR) bit is set high if the GPIC is an initiator and asserts or detects a parity error on the PERRB signal while the PERREN bit is set in the Command register. The DPR bit is cleared by the PCI Host. DVSLT[1:0]: The Device Select Timing (DEVSLT) bits specify the allowable timings for the assertion of DEVSELB by the GPIC as a target. These are encoded as 00B for fast, 01B for medium, 10B for slow and 11B is not used. The GPIC allows for medium timing. TABT: The Target Abort (TABT) bit is set high by the GPIC when as a target, it terminates a transaction with a target abort. The TABT bit is cleared by the PCI Host. RTABT: The Received Target Abort (RTABT) bit is set high by the GPIC when as an initiator, its transaction is terminated by a target abort. The RTABT bit is cleared by the PCI Host. MABT: The Master Abort (MABT) bit is set high by the GPIC when as an initiator, its transaction is terminated by a master abort and a special cycle was not in progress. The MABT bit is cleared by the PCI Host.
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SERR: The System Error (SERR) bit is set high whenever the GPIC asserts the SERRB output. The SERR bit is cleared by the PCI Host. PERR: The Parity Error (PERR) bit is set high whenever the GPIC detects a parity error, even if parity error handling is disabled by clearing PERREN in the Command register. The PERR bit is cleared by the PCI Host.
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Register 0x08 : Revision Identifier/Class Code Bit
Bit 31 to Bit 24 Bit 23 to Bit 16 Bit 15 to Bit 8 Bit 7 to Bit 0 REVID[7:0]: The Revision Identifier (REVID[7:0]) bits specify a device specific revision identifier and are chosen by PMC-Sierra. CCODE[23:0]: The class code (CCODE[23:0]) bits are divided into three groupings: CCODE[23:16] define the base class of the device, CCODE[15:8] define the sub-class of the device and CCODE[7:0] specify a register specific programming interface.
Type
R
Function
CCODE[23:16]
Default
02H
R
CCODE[15:8]
80H
R
CCODE[7:0]
00H
R
REVID[7:0]
02H
Note:
Base Class Code: Sub-Class Code: Register Class Code: 02H 80H 00H Network Controller Other Controllers None defined.
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Register 0x0C : Cache Line Size/Latency Timer/Header Type Bit
Bit 31 to Bit 24 Bit 23 Bit 22 to Bit 16 Bit 15 to Bit 8 Bit 7 to Bit 0 CLSIZE[7:0]: The Cache Line Size (CLSIZE[7:0]) bits specify the size of the system cacheline in units of dwords. The GPIC uses this value to determine the type of read command to issue in a Master Read transfer. If the transfer size is equal to one, the GPIC will issue a Memory Read command. If the transfer size is equal to or less than the CLSIZE, the GPIC will issue a Memory Read Line command. For transfers larger than CLSIZE, the GPIC issues a Memory Read Multiple command. LT[7:0]: The Latency Timer (LT[7:0]) bits specify, in units of the PCI clock, the value of the Latency Timer for the GPIC. At reset the value is zero. The value of the LT is application specific and should be programmed by software. HDTYPE[6:0]: The Header Type (HDTYPE[7:0]) bits specify the layout of the base address registers. Only the 00H encoding is supported. MLTFNC: The Multi-Function (MLTFNC) bit specifies if the GPIC supports multiple PCI functions. If this bit is set low, the device only supports one function and if the bit is set high, the device supports multi-functions. The MLTFNC bit is set low to indicate the GPIC only supports one PCI function.
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Type
R
Function
Reserved
Default
00H
R R
MLTFNC HDTYPE[6:0]
0 00H
R/W
LT[7:0]
00H
R/W
CLSIZE
00H
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Register 0x10 : CBI Memory Base Address Register Bit
Bit 31 to Bit 13 Bit 12 to Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type
R/W
Function
BSAD[27:9]
Default
00000H
R
BSAD[8:0]
000H
R R R R
PRFTCH TYPE[1] TYPE[0] MSI
0 0 0 0
The GPIC supports memory mapping only. At boot-up the internal registers space is mapped to memory space. The device driver can disable memory space through the PCI Configuration Command register. MSI: MSI is forced low to indicate that the internal registers map into memory space. TYPE[1:0]: The TYPE field indicates where the internal registers can be mapped. The encoding 00B indicates the registers may be located anywhere in the 32 bit address space, 01B indicates that the registers must be mapped below 1 Meg in memory space, 10B indicates the base register is 64 bits and the encoding 11B is reserved. The TYPE field is set to 00B to indicate that the CBI registers can be mapped anywhere in the 32 bit address space. PRFTCH: The Prefetchable (PRFTCH) bit is set if there are no side effects on reads and data is returned on all the lanes regardless of the byte enables. Otherwise the bit is cleared. TSBs contain registers, such as interrupt status registers, in which bits are cleared on a read. If the PCI Host is caching data there is a possibility an interrupt status could be lost if data is prefetched, but the cache is flushed and the data is not used. The PRFTCH bit is forced low to indicate that prefetching of data is not supported for internal registers.
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BSAD[27:0]: The Base Address (BSAD[27:0]) bits defines the size and location of the memory space required for the CBI registers. The BSAD[27:0] bits correspond to the most significant 28 bits of the PCI address space. The size of the address space required can be determined by writing all ones to Base Address register and then reading from it. By scanning the returned value from the least significant bit upwards, the size of the required address space can be determined. The binary weighted value of the first one bit found (after the configuration bits) indicates the required amount of space. The BSAD[8:0] bits are forced low to indicate that the CBI registers require 8K bytes of memory space. After determining the memory requirements of the CBI registers, the PCI Host can map them to its desired location by modifying the BSAD[27:9] bits in the Base Address register.
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Register 0x3C : Interrupt Line / Interrupt Pin / MIN_GNT / MAX_LAT Bit
Bit 31 to Bit 24 Bit 23 to Bit 16 Bit 15 to Bit 8 Bit 7 to Bit 0 INTLNE[7:0]: The Interrupt Line (INTLNE[7:0]) field is used to indicate interrupt line routing information. The values in this register are system specific and set by the PCI Host. INTPIN[7:0]: The Interrupt Pin (INTPIN[7:0]) field is used to specify the interrupt pin the GPIC uses. Since the GPIC will use INTAB on the PCI bus, the value in this register is set to one. MINGNT[7:0]: The Minimum Grant (MINGNT[7:0]) field specifies how long of a burst period the bus master needs (in increments of 250 nsec). MAXLAT[7:0]: The Maximum Latency (MAXLAT[7:0]) field specifies how often a bus master needs access to the PCI bus (in increments of 250 nsec).
Type
R
Function
MAXLAT[7:0]
Default
0FH
R
MINGNT[7:0]
05H
R
INTPIN[7:0]
01H
R/W
INTLNE[7:0]
00H
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12
TEST FEATURES DESCRIPTION
The FREEDM-84P672 also supports a standard IEEE 1149.1 five signal JTAG boundary scan test port for use in board testing. All device inputs may be read and all device outputs may be forced via the JTAG test port.
12.1 Test Mode Registers
Test mode registers are used to apply test vectors during production testing of the FREEDM-84P672. Production testing is enabled by asserting the PMCTEST pin. During production tests, FREEDM-84P672 registers are selected by the TA[12:0] pins. The address of a register on TA[12:0] is identical to the PCI offset of that register when production testing is disabled (PMCTEST low). Read accesses are enabled by asserting TRDB low while write accesses are enabled by asserting TWRB low. Test mode register data is conveyed on the TDAT[15:0] pins. Test mode registers (as opposed to normal mode registers) are selected when TA[12]/TRS is set high.
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Table 40 - Test Mode Register Memory Map Address TA[12:0]
0x0000 - 0x07FC 0x0800 - 0x107C 0x1080 - 0x10FC 0x1100 - 0x11FC 0x1200 - 0x123C 0x1240 - 0x127C 0x1280 - 0x12FC 0x1300 - 0x137C 0x1380 - 0x13BC 0x13C0 - 0x13FC 0x1400 - 0x14FC 0x1500 - 0x151C 0x1520 - 0x15BC 0x15C0 - 0x15FC 0x1600 - 0x167C 0x1680 - 0x16FC 0x1700 - 0x17FC 0x1800 - 0x18FC 0x1900 - 0x19FC 0x1A00 - 0x1AFC 0x1B00 - 0x1BFC 0x1C00 - 0x1CFC 0x1D00 - 0x1DFC 0x1E00 - 0x1FFC
Register
Normal Mode Registers Reserved GPIC Test Registers RCAS Test Registers RHDL Test Registers Reserved RMAC Test Registers TMAC Test Registers THDL Test Registers Reserved TCAS Test Registers PMON Test Registers Reserved SBI EXTRACT Test Registers Reserved SBI INSERT Test Registers Reserved SBI PISO#1 Test Registers SBI PISO#2 Test Registers SBI PISO#3 Test Registers SBI SIPO#1 Test Registers SBI SIPO#2 Test Registers SBI SIPO#3 Test Registers Reserved
Notes on Test Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product,
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unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. Writable test mode register bits are not initialized upon reset unless otherwise noted.
12.2 JTAG Test Port
The FREEDM-84P672 JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section.
Table 41 - Instruction Register Length - 3 bits Instructions
EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS
Selected Register
Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass
Instruction Code IR[2:0]
000 001 010 011 100 101 110 111
12.2.1 Identification Register
Length - 32 bits Version number - 2H Part Number - 7384H Manufacturer's identification code - 0CDH
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Device identification - 273840CDH
12.2.2 Boundary Scan Register
The boundary scan register is made up of 365 boundary scan cells, divided into input observation (in_cell), output (out_cell), and bi-directional (io_cell) cells. These cells are detailed in the following pages. The first 32 cells form the ID code register, and carry the code 273840CDH. The cells are arranged as follows:
Table 42 - Boundary Scan Chain Pin/ Enable
Unconnected Unconnected Unconnected Unconnected FASTCLK Logic 0 SPE1_EN SPE2_EN SPE3_EN TD_OEN[0] TD[0] TCLK[0] TD_OEN[1] TD[1] TCLK[1] TD_OEN[2] TD[2] TCLK[2] C1FPOUT_OEN C1FPOUT REFCLK
Register Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Cell Type
OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL
Device I.D.
-
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Pin/ Enable
APL_OEN APL DPL AV5_OEN AV5 DV5 ADP_OEN ADP DDP AACTIVE_OEN AACTIVE C1FP Logic 0 Logic 0 ADATA_OEN[0] ADATA[0] DDATA[0] ADATA_OEN[1] ADATA[1] DDATA[1] ADATA_OEN[2] ADATA[2] DDATA[2] ADATA_OEN[3] ADATA[3] DDATA[3] ADATA_OEN[4] ADATA[4] DDATA[4]
Register Bit
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
Cell Type
OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL
299
Device I.D.
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Pin/ Enable
ADATA_OEN[5] ADATA[5] DDATA[5] ADATA_OEN[6] ADATA[6] DDATA[6] ADATA_OEN[7] ADATA[7] DDATA[7] Logic 0 Logic 0 TDAT_OEN[0] TDAT[0] AJUST_REQ TDAT_OEN[1] TDAT[1] ADETECT[0] TDAT_OEN[2] TDAT[2] ADETECT[1] TDAT_OEN[3] TDAT[3] Logic 0 TDAT_OEN[4] TDAT[4] Logic 0 TDAT_OEN[5] TDAT[5] Logic 0
Register Bit
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
Cell Type
OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL
300
Device I.D.
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Pin/ Enable
TDAT_OEN[6] TDAT[6] Logic 0 TDAT_OEN[7] TDAT[7] Logic 0 Logic 0 Logic 0 TDAT_OEN[8] TDAT[8] Logic 0 TDAT_OEN[9] TDAT[9] Logic 0 TDAT_OEN[10] TDAT[10] Logic 0 TDAT_OEN[11] TDAT[11] Logic 0 TDAT_OEN[12] TDAT[12] Logic 0 TDAT_OEN[13] TDAT[13] Logic 0 TDAT_OEN[14] TDAT[14] Logic 0
Register Bit
79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107
Cell Type
OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL IN_CELL
301
Device I.D.
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Pin/ Enable
TDAT_OEN[15] TDAT[15] Logic 0 Logic 0 Unconnected Unconnected PMCTEST Logic 0 Logic 0 Logic 0 M66EN AD_OEN[0] AD[0] AD_OEN[1] AD[1] AD_OEN[2] AD[2] AD_OEN[3] AD[3] AD_OEN[4] AD[4] AD_OEN[5] AD[5] AD_OEN[6] AD[6] AD_OEN[7] AD[7] CBEB_OEN[0] CBEB[0]
Register Bit
108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136
Cell Type
OUT_CELL IO_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL
302
Device I.D.
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Pin/ Enable
AD_OEN[8] AD[8] AD_OEN[9] AD[9] AD_OEN[10] AD[10] AD_OEN[11] AD[11] AD_OEN[12] AD[12] AD_OEN[13] AD[13] AD_OEN[14] AD[14] AD_OEN[15] AD[15] CBEB_OEN[1] CBEB[1] PAR_OEN PAR SERRB_OEN SERRB PERRB_OEN PERRB LOCKB STOPB_OEN STOPB DEVSELB_OEN DEVSELB
Register Bit
137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165
Cell Type
OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL
303
Device I.D.
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Pin/ Enable
TRDYB_OEN TRDYB IRDYB_OEN IRDYB FRAMEB_OEN FRAMEB CBEB_OEN[2] CBEB[2] AD_OEN[16] AD[16] AD_OEN[17] AD[17] AD_OEN[18] AD[18] AD_OEN[19] AD[19] AD_OEN[20] AD[20] AD_OEN[21] AD[21] AD_OEN[22] AD[22] AD_OEN[23] AD[23] IDSEL CBEB_OEN[3] CBEB[3] AD_OEN[24] AD[24]
Register Bit
166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194
Cell Type
OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL
304
Device I.D.
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Pin/ Enable
AD_OEN[25] AD[25] AD_OEN[26] AD[26] AD_OEN[27] AD[27] AD_OEN[28] AD[28] AD_OEN[29] AD[29] AD_OEN[30] AD[30] AD_OEN[31] AD[31] REQB_OEN REQB Logic 0 GNTB PCICLK Logic 0 PCICLKO_OEN PCICLKO Logic 0 PCIINTB_OEN PCIINTB Logic 0 Logic 0 Logic 0 Logic 0
Register Bit
195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223
Cell Type
OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL IO_CELL IN_CELL IN_CELL IN_CELL IN_CELL
305
Device I.D.
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Pin/ Enable
Logic 0 Logic 0 Logic 0 Logic 0 Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected
Register Bit
224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252
Cell Type
IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL
306
Device I.D.
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Pin/ Enable
Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0
Register Bit
253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281
Cell Type
IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
307
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Pin/ Enable
Logic 1 Logic 1 Logic 1 Logic 1 Unconnected Unconnected Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 TA[12] Logic 0 Logic 0 Logic 0 TWRB Logic 0 TRDB Logic 0
Register Bit
282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310
Cell Type
IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
308
Device I.D.
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Pin/ Enable
TA[11] Logic 0 TA[10] Logic 0 TA[9] Logic 0 TA[8] Logic 0 TA[7] Logic 0 TA[6] Logic 0 Logic 0 Logic 0 TA[5] RSTB Logic 0 TA[4] Logic 0 TA[3] Logic 0 TA[2] Logic 0 TA[1] Logic 0 TA[0] Logic 0 Logic 0 Logic 0
Register Bit
311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339
Cell Type
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL
309
Device I.D.
1 0 1 1 0 0 1
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Pin/ Enable
Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 SYSCLK Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 RCLK[2] RD[2] RCLK[1] RD[1] RCLK[0] RD[0] Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 TDO TDI TCK TMS
Register Bit
340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364
Cell Type
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL TAP Output TAP Input TAP Clock TAP Input
310
Device I.D.
1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 1 1 0 0 1 0 0 -
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Pin/ Enable
TRSTB
Register Bit
Cell Type
TAP Input
Device I.D.
-
Notes:
1. Register bit 364 is the first bit of the scan chain (closest to TDI). 2. Enable cell pinname_OEN, tristates pin pinname when set high. 3. Cells `Logic 0' and `Logic 1' are Input Observation cells whose input pad is bonded to VSS or VDD internally. 4. Cells titled `Unconnected' are Output or Bi-directional cells whose pad is unconnected to the device package. In the case of bi-directional cells, the pad always drives (i.e. never tri-states) and the pad input is the same logic value as the pad output.
Figure 16 - Input Observation Cell (IN_CELL)
IDCODE Scan Chain Out INPUT to internal logic
Input Pad
G1 G2 SHIFT-DR
I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
Scan Chain In
D C
In this diagram and those that follow, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexor in the center of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the table above.
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Figure 17 - Output Cell (OUT_CELL)
Scan Chain Out EXTEST Output or Enable from system logic IDCODE SHIFT-DR
G1 1 G1 G2 12 1 2 MUX 12 12 D C D C 1
Output or Enable
MUX
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
Figure 18 - Bi-directional Cell (IO_CELL)
Scan Chain Out INPUT to internal logic
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin I.D. code bit CLOCK-DR UPDATE-DR Scan Chain In
G1 1 G1 G2 12 1 2 MUX 12 12 1
MUX
OUTPUT to pin
D C
D C
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Figure 19 - Layout of Output Enable and Bi-directional Cells
Scan Chain Out OUTPUT ENABLE from internal logic (0 = drive)
OUT_CELL
Scan Chain In Scan Chain Out INPUT to internal logic OUTPUT from internal logic
IO_CELL
I/O PAD
Scan Chain In
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13
OPERATIONS
This section presents operating details for the JTAG boundary scan feature.
13.1 JTAG Support
The FREEDM-84P672 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below.
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Figure 20 - Boundary Scan Architecture
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a single bit delay from primary input, TDI to primary output , TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register placed in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be
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sampled and shifted out on primary output TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital outputs.
TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below.
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Figure 21 - TAP Controller Finite State Machine
TRSTB=0 Test-Logic-Reset 1 0 1 Run-Test-Idle 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 0 1 Select-DR-Scan 0 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 0 1 1 Select-IR-Scan 0 1
All transitions dependent on input TMS
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Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction.
Run-Test-Idle
The run test/idle state is used to execute tests.
Capture-DR
The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK.
Shift-DR
The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
Update-DR
The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK.
Capture-IR
The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK.
Shift-IR
The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
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Update-IR
The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused.
Boundary Scan Instructions
The following is a description of the standard instructions. Each instruction selects a serial test data register path between input, TDI and output, TDO.
BYPASS
The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device.
EXTEST
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is place between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state.
SAMPLE
The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state.
IDCODE
The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state.
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STCTEST
The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out output, TDO using the Shift-DR state.
INTEST
The internal test instruction is used to exercise the device's internal core logic. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Update-DR state, patterns shifted in on input, TDI are used to drive primary inputs. During the Capture-DR state, primary outputs are sampled and loaded into the boundary scan register.
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14
FUNCTIONAL TIMING
14.1 SBI DROP BUS Interface Timing Figure 22 - T1/E1 DROP BUS Functional Timing
REFCLK C1FP DDATA[7:0] DPL DV5 DDP C1
*** *** *** *** *** ***
V3
V3
V3 DS0#4. V5 DS0#9.
Figure 22 illustrates the operation of the SBI DROP BUS, using a negative justification on the second to last V3 octet as an example. The justification is indicated by asserting DPL high during the V3 octet. The timing diagram also shows the location of one of the tributaries by asserting DV5 high during the V5 octet.
Figure 23 - DS3 DROP BUS Functional Timing
REFCLK C1FP DDATA[7:0] DPL DV5 DDP C1
*** *** *** *** *** ***
H3
H3
H3
DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1
Figure 23 shows three DS-3 tributaries mapped onto the SBI bus. A negative justification is shown for DS-3 #2 during the H3 octet with DPL asserted high. A positive justification is shown for DS-3#1 during the first DS-3#1 octet after H3 which has DPL asserted low.
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14.2 SBI ADD BUS Interface Timing Figure 24 - DS3 Add Bus Adjustment Request Functional Timing
REFCLK C1FP ADATA[7:0] APL AV5 ADP AJUST_REQ AACTIVE C1 *** *** *** *** *** *** *** *** H3 H3 H3
DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1
Figure 24 illustrates the operation of the SBI ADD BUS, using positive and negative justification requests as an example. (The responses to the justification requests would take effect during the next multi-frame.) The negative justification request occurs on the DS-3#3 tributary when AJUST_REQ is asserted high during the H3 octet. The positive justification occurs on the DS-3#2 tributary when AJUST_REQ is asserted high during the first DS-3#2 octet after the H3 octet. The AACTIVE signal is shown for the case in which FREEDM84P672 is only driving DS-3#2 onto the SBI ADD bus.
14.3 Receive Link Timing
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals is shown in Figure 25. The receive data is viewed as a contiguous serial stream. There is no concept of time-slots or framing. Every eight bits are grouped together into a byte with arbitrary alignment. The first bit received (B1 in Figure 25) is deemed the most significant bit of an octet. The last bit received (B8) is deemed the least significant bit. Bits that are to be processed by the FREEDM84P672 are clocked in on the rising edge of RCLK[n]. Bits that should be ignored (X in Figure 25) are squelched by holding RCLK[n] quiescent. In Figure 25, the quiescent period is shown to be a low level on RCLK[n]. A high level, effected by extending the high phase of the previous valid bit, is also acceptable. Selection of bits for processing is arbitrary and is not subject to any byte alignment nor frame boundary considerations.
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Figure 25 - Receive Link Timing
RCLK[n] RD[n]
14.4 Transmit Link Timing
B1 B2 B3 B4 X B5 X X X B6 B7 B8 B1 X
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals is shown in Figure 26. The transmit data is viewed as a contiguous serial stream. There is no concept of time-slots or framing. Every eight bits are grouped together into a byte with arbitrary byte alignment. Octet data is transmitted from most significant bit (B1 in Figure 26) and ending with the least significant bit (B8 in Figure 26). Bits are updated on the falling edge of TCLK[n]. A transmit link may be stalled by holding the corresponding TCLK[n] quiescent. In Figure 26, bits B5 and B2 are shown to be stalled for one cycle while bit B6 is shown to be stalled for three cycles. In Figure 26, the quiescent period is shown to be a low level on TCLK[n]. A high level, effected by extending the high phase of the previous valid bit, is also acceptable. Gapping of TCLK[n] can occur arbitrarily without regard to byte nor frame boundaries.
Figure 26 - Transmit Link Timing
TCLK[n] TD[n]
14.5 PCI Interface
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2
A PCI burst read cycle is shown In Figure 27. The cycle is valid for target and initiator accesses. The target is responsible for incrementing the address during the data burst. The 'T' symbol stands for a turn around cycle. A turn around cycle is required on all signals which can be driven by more than one agent. During Clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with the read command. In the example below, the command would indicate a burst read. The IRDYB, TRDYB and DEVSELB signals are in turnaround mode (i.e. no agent is driving the signals for this clock cycle). This cycle on the PCI bus is called the address phase.
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During Clock 2, the initiator ceases to drive the AD[31:0] bus in order that the target can drive it in the next cycle. The initiator also drives the C/BEB[3:0] lines with the byte enables for the read data. IRDYB is driven active by the initiator to indicate it is ready to accept the data transfer. All subsequent cycles on the PCI bus are called data phases. During Clock 3, the target claims the transaction by driving DEVSELB active. It also places the first data word onto the AD[31:0] bus and drives TRDYB to indicate to the initiator that the data is valid. During Clock 4, the initiator latches in the first data word. The target negates TRDYB to indicate to the initiator that it is not ready to transfer another data word. During Clock 5, the target places the second data word onto the AD[31:0] bus and drives TRDYB to indicate to the initiator that the data is valid. During Clock 6, the initiator latches the second data word and negates IRDYB to indicate to the target that it is not ready for the next transfer. The target shall drive the third data word until the initiator accepts it. During Clock 7, the initiator asserts IRDYB to indicate to the target it is ready for the third data word. It also negates FRAMEB since this shall be the last transfer. During Clock 8, the initiator latches in the last word and negates IRDYB. The target, having seen FRAMEB negated in the last clock cycle, negates TRDYB and DEVSELB. All of the above signals shall be driven to their inactive state in this clock cycle, except for FRAMEB which shall be tristated. The target shall stop driving the AD[31:0] bus and the initiator shall stop driving the C/BEB[3:0] bus; this shall be the turnaround cycle for these signals.
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Figure 27 - PCI Read Cycle
1 2 3 4 5 6 7 8
T
9
PCICLK FRAMEB AD[31:0] C/BEB[3:0] IRDYB TRDYB DEVSELB
Address
Bus Cmd T T T T
Data 1
Data 2 Byte Enable
Data 3 Byte Enable
T T
Byte Enable
A PCI burst write transaction is shown in Figure 28. The cycle is valid for target and initiator accesses. The target is responsible for incrementing the address for the duration of the data burst. The 'T' symbol stands for a turn around cycle. A turn around cycle is required on all signals which can be driven by more than one agent. During clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with the write command (in the above example the command would indicate a burst write). The IRDYB, TRDYB and DEVSELB signals are in turnaround mode (no agent is driving the signals for this clock cycle). This cycle on the PCI bus is called the address phase. During clock 2, the initiator ceases to drive the address onto the AD[31:0] bus and starts driving the first data word. The initiator also drives the C/BEB[3:0] lines with the byte enables for the write data. IRDYB is driven active by the initiator to indicate it is ready to accept the data transfer. The target claims the transaction by driving DEVSELB active and drives TRDYB to indicate to the initiator that it is ready to accept the data. All subsequent cycles on the PCI bus are called data phases. During clock 3, the target latches in the first data word. The initiator starts to drive the next data word onto the AD[31:0] lines. During clock 4, the target latches in the second data word. Both the initiator and the target indicate that they are not ready to transfer any more data by negating the ready lines.
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During clock 5, the initiator is ready to transfer the next data word so it drives the AD[31:0] lines with the third data word and asserts IRDYB. The initiator negates FRAMEB since this is the last data phase of this cycle. The target is still not ready so a wait state shall be added. During clock 6, the target is still not ready so another wait state is added. During clock 7, the target asserts TRDYB to indicate that it is ready to complete the transfer. During clock 8, the target latches in the last word and negates TRDYB and DEVSELB, having seen FRAMEB negated previously. The initiator negates IRDYB. All of the above signals shall be driven to their inactive state in this clock cycle except for FRAMEB which shall be tristated.
Figure 28 - PCI Write Cycle
1 2 3 4 5 6 7 8 9
PCICLK FRAMEB AD[31:0] C/BEB[3:0] IRDYB TRDYB DEVSELB
Address Data 1 Data 2 Data 3 Byte Enable
T T T
Bus Cmd Byte En Byte En T T T
The PCI Target Disconnect (Figure 29) illustrates the case when the target wants to prematurely terminate the current cycle. Note, when the FREEDM-84P672 is the target, it never prematurely terminates the current cycle. A target can terminate the current cycle by asserting the STOPB signal to the initiator. Whether data is transferred or not depends on the state of the ready signals at the time that the target disconnects. If the FREEDM-84P672 is the initiator and the target terminates the current access, the FREEDM-84P672 will retry the access after two PCI bus cycles. During clock 1, an access is in progress.
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During clock 2, the target indicates that it wishes to disconnect by asserting STOPB. Data may be transferred depending on the state of the ready lines. During clock 3, the initiator negates FRAMEB to signal the end of the cycle. During clock 4, the target negates STOPB and DEVSELB in response to the FRAMEB signal being negated.
Figure 29 - PCI Target Disconnect
1 2 3 4 5 6
PCICLK FRAMEB STOPB DEVSELB
T
The PCI Target Abort Diagram (Figure 30) illustrates the case when the target wants to abort the current cycle. Note, when the FREEDM-84P672 is the target, it never aborts the current cycle. A target abort is an indication of a serious error and no data is transferred. A target can terminate the current cycle by asserting STOPB and negating DEVSELB. If the FREEDM-84P672 is the initiator and the target aborts the current access, the abort condition is reported to the PCI Host. During clock 1, a cycle is in progress. During clock 2, the target negates DEVSELB and TRDYB and asserts STOPB to indicate an abort condition to the initiator. During clock 3, the initiator negates FRAMEB in response to the abort request. During clock 4, the target negates STOPB signal in response to the FRAMEB signal being negated.
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Figure 30 - PCI Target Abort
1 2 3 4 5 6
PCICLK FRAMEB TRDYB STOPB DEVSELB The PCI Bus Request Cycle Diagram (Figure 31) illustrates the case when the initiator is requesting the bus from the bus arbiter. When the FREEDM-84P672 is the initiator, it requests the PCI bus by asserting its REQB output to the central arbiter. The arbiter grants the bus to the FREEDM-84P672 by asserting the GNTB line. The FREEDM-84P672 will wait till both the FRAMEB and IRDYB lines are idle before starting its access on the PCI bus. The arbiter can remove the GNTB signal at any time, but the FREEDM-84P672 will complete the current transfer before relinquishing the bus.
T
Figure 31 - PCI Bus Request Cycle
1 2 3 4 5 6
PCICLK REQB GNTB FRAMEB
T
The PCI Initiator Abort Termination Diagram (Figure 32) illustrates the case when the initiator aborts a transaction on the PCI bus. An initiator may terminate a cycle if no target claims it within five clock cycles. A target may not have responded because it was incapable of dealing with the request or a bad address was generated by the initiator. IRDYB must be valid one clock after FRAMEB is deasserted as in a normal cycle. When the
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FREEDM-84P672 is the initiator and aborts the transaction, it reports the error condition to the PCI Host.
Figure 32 - PCI Initiator Abort Termination
1 2 3 4 5 6 7
PCICLK FRAMEB TRDYB IRDYB DEVSELB
T T T T
The PCI Exclusive Lock Cycle Diagram (Figure 33) illustrates the case when the current initiator locks the PCI bus. The FREEDM-84P672 will never initiate an lock, but will behave appropriately when acting as a target. During clock 1, the present initiator has gained access of the LOCKB signal and the PCI bus. The first cycle of a locked access must be a read cycle. The initiator asserts FRAMEB and drives the address of the target on the AD[31:0] lines. During clock 2, the present initiator asserts LOCKB to indicate to the target that a locked cycle is in progress. During clock 3, the target samples the asserted LOCKB signal and marks itself locked. The data cycle has to complete in order for the lock to be maintained. If for some reason the cycle was aborted, the initiator must negate LOCKB. During clock 4, the data transfer completes and the target is locked. During clock 6, another initiator may use the PCI bus but it cannot use the LOCKB signal. If the other initiator attempts to access the locked target that it did not lock, the target would reject the access. During clock 7, the same initiator that locked this target accesses the target. The initiator asserts FRAMEB and negates LOCKB to re-establish the lock. During clock 8, the target samples LOCKB deasserted and locks itself.
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During clock 9, the initiator does not want to continue the lock so it negates LOCKB. The target samples LOCKB and FRAMEB deasserted it removes its lock.
Figure 33 - PCI Exclusive Lock Cycle
1 2 3 4 5 6 7 8 9
PCICLK FRAMEB AD[31:0] LOCKB IRDYB TRDYB DEVSELB
Address
T T T T T T T T T T T
Data
Address
Data
Fast back-to-back transactions are used by an initiator to conduct two consecutive transactions on the PCI bus without the required idle cycle between them. This can only occur if there is a guarantee that there will be no contention between the initiator or targets involved in the two transactions. In the first case, an initiator may perform fast back-to-back transactions if the first transaction is a write and the second transaction is to the same target. All targets must be able to decode the above transaction. In the second case, all of the targets on the PCI bus support fast back-to-back transactions, as indicated in the PCI Status configuration register. The FREEDM-84P672 only supports the first type of fast back-to-back transactions and is shown in Figure 34. During clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with the write command. In this example the command would indicate a single write. The IRDYB, TRDYB and DEVSELB signals are in turnaround mode and are not being driven for this clock cycle. This cycle on the PCI bus is called the address phase. During clock 2, the initiator ceases to drive the address onto the AD[31:0] bus and starts driving the data element. The initiator also drives the C/BEB[3:0] lines with the byte enables for the write data. IRDYB is driven active by the initiator to indicate that the data is valid.
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The initiator negates FRAMEB since this the last data phase of this cycle. The target claims the transaction by driving DEVSELB active and drives TRDYB to indicate to the initiator that it is ready to accept the data. During clock 3, the target latches in the data element and negates TRDYB and DEVSELB, having seen FRAMEB negated previously. The initiator negates IRDYB and drives FRAMEB to start the next cycle. It also drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with the write command. In this example the command would indicate a burst write. During clock 4, the initiator ceases to drive the address onto the AD[31:0] bus and starts driving the first data element. The initiator also drives the C/BEB[3:0] lines with the byte enables for the write data. IRDYB is driven active by the initiator to indicate that the data is valid. The target claims the transaction by driving DEVSELB active and drives TRDYB to indicate to the initiator that it is ready to accept the data. During clock 5, the initiator is ready to transfer the next data element so it drives the AD[31:0] lines with the second data element. The initiator negates FRAMEB since this is the last data phase of this cycle. The target accepts the first data element and negates TRDYB to indicate its is not ready for the next data element. During clock 6, the target is still not ready so a wait state shall be added. During clock 7, the target asserts TRDYB to indicate that it is ready to complete the transfer. During clock 8, the target latches in the last element and negates TRDYB and DEVSELB, having seen FRAMEB negated previously. The initiator negates IRDYB. All of the above signals shall be driven to their inactive state in this clock cycle, except for FRAMEB which shall be tristated. The target stops driving the AD[31:0] bus and the initiator stops driving the C/BEB[3:0] bus. This shall be the turnaround cycle for these signals.
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Figure 34 - PCI Fast Back to Back
1 2 3 4 5 6 7 8 9
PCICLK FRAMEB AD[31:0] C/BEB[3:0] IRDYB TRDYB DEVSELB
Address Data Address Data Data Byte Enable
T T T
Bus Cmd Byte En Bus Cmd T T T
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15
ABSOLUTE MAXIMUM RATINGS
Maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal operating conditions.
Table 43 - FREEDM-84P672 Absolute Maximum Ratings
Case Temperature under Bias Storage Temperature Supply Voltage (+3.3 Volt VDD3.3) Supply Voltage (+2.5 Volt VDD2.5) Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Absolute Maximum Junction Temperature -40C to +85C -40C to +125C -0.3V to +4.6V -0.3V to +3.5V -0.3V to VDD3.3 + 0.3V 1000 V 100 mA 20 mA +230C +150C
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16
D.C. CHARACTERISTICS (TA = -40C to +85C, VDD3.3 = 3.0 to 3.6 V, VDD2.5 = 2.3 to 2.7 V) Table 44 - FREEDM-84P672 D.C. Characteristics
Symbol
VDD3.3 VDD2.5 VIL VIL
Parameter
3.3V Power Supply 2.5V Power Supply PCI Input Low Voltage (Bidirs) PCI Input Low Voltage (Inputs)
Min
3.0 2.3 -0.5 -0.5
Typ
3.3 2.5
Max
3.6 2.7 0.8 0.6
Units
Volts Volts Volts Volts Note 4. Note 4.
Conditions
Guaranteed Input LOW Voltage for PCI bidirs. Guaranteed Input LOW Voltage for PCI inputs (PCICLK, IDSEL, LOCKB, GNTB, M66EN). Guaranteed Input HIGH Voltage for PCI inputs/bidirs. IOL = -8 mA for all outputs except TDO, where IOL = -4 mA. Note 3. IOH = 8 mA for all outputs except TDO, where IOH = 4 mA. Note 3.
VIH
PCI Input High Voltage Output or Bidirectional Low Voltage Output or Bidirectional High Voltage Schmitt Triggered Input High Voltage Schmitt Triggered Input Low Voltage Input Low Current Input High Current Input Low Current Input High Current Input Capacitance
0.5 * VDD3.3
VDD3.3 + 0.5 0.4
Volts
VOL
Volts
VOH
2.4
Volts
VT+ VTIILPU IIHPU IIL IIH CIN
2.0 -0.2 +10 -10 -10 -10 45 0 0 0 5
VDD3.3 + 0.5 0.6 +100 +10 +10 +10
Volts Volts A A A A pF VIL = GND, Notes 1, 3, 4. VIH = VDD, Notes 1, 3 VIL = GND, Notes 2, 3 VIH = VDD, Notes 2, 3 Excludes package. Package typically 2 pF. Note 4.
334
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Symbol
COUT
Parameter
Output Capacitance Bi-directional Capacitance Pin Inductance Operating Current.
Min
Typ
5
Max
Units
pF
Conditions
All pins. Excludes package. Package typically 2 pF. Note 4. All pins. Excludes package. Package typically 2 pF. Note 4. All pins. Note 4. VDD2.5 = 2.7V, Outputs Unloaded. All 3 SPEs on SBI interface active. Note 4.
CIO
5
pF
LPIN IDDOP
2 500
nH mA
Notes on D.C. Characteristics:
1. Input pin or bi-directional pin with internal pull-up resistor. 2. Input pin or bi-directional pin without internal pull-up resistor. 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. Typical values are given as a design aid. The product is not tested to the typical values given in the data sheet.
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17
FREEDM-84P672 TIMING CHARACTERISTICS (TA = -40C to +85C, VDD3.3 = 3.0 to 3.6 V, VDD2.5 = 2.3 to 2.7 V) Table 45 - Clocks and SBI Frame Pulse (Figure 35) Symbol Description
REFCLK Frequency REFCLK Duty Cycle FASTCLK Frequency (51.84 MHz) FASTCLK Frequency (44.928 MHz) FASTCLK Frequency (66 MHz) FASTCLK Duty Cycle SYSCLK Frequency SYSCLK Duty Cycle TSC1FP THC1FP TPC1FPOUT C1FP Set-Up Time to REFCLK C1FP Hold Time to REFCLK REFCLK to C1FPOUT Valid
Min
19.44 -50 ppm 40 51.84 -50 ppm 44.928 -50 ppm 66 -50 ppm 40 45 -50 ppm 40 4 1 2
Max
19.44 +50 ppm 60 51.84 +50 ppm 44.928 +50 ppm 66 +50 ppm 60 45 +50 ppm 60
Units
MHz % MHz MHz MHz % MHz % ns ns
20
ns
Notes on Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Notes on Output Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum and minimum output propagation delays are measured with a 50 pF load on all the outputs except TD[2:0] which are measured with a 20 pF load and the PCI outputs/bidirs which are measured with a 10 pF load. Maximum propagation delay for TD[2:0] increases by typically 1 ns for each 10 pF of extra load. 3. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current.
Figure 35 - SBI Frame Pulse Timing
REFCLK tS C 1FP C1FP tH C1FP
tP C1FPOUT C1FPO UT
Table 46 - SBI DROP BUS (Figure 36) Symbol
tSSBIDROP tHSBIDROP
Description
All SBI DROP BUS Inputs Set-Up Time to REFCLK All SBI DROP BUS Inputs Hold Time to REFCLK
Min
4 1
Max
Units
ns ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Figure 36 - SBI DROP BUS Timing
REFCLK
tS SBIDROP DDATA[7:0] DDP, DPL DV5
tH SBIDROP
Table 47 - SBI ADD BUS (Figure 37 to Figure 38) Symbol
tSSBIADD tHSBIADD tPAACTIVE tPSBIADD tZSBIADD tPOUTEN tZOUTEN
Description
AJUST_REQ Set-Up Time to REFCLK AJUST_REQ Hold Time to REFCLK REFCLK to AACTIVE Valid REFCLK to All SBI ADD BUS Outputs (except AACTIVE) Valid REFCLK to All SBI ADD BUS Outputs (except AACTIVE) Tristate ADETECT[1] and ADETECT[0] low to All SBI ADD BUS Outputs (except AACTIVE) Valid ADETECT[1] or ADETECT[0] high to All SBI ADD BUS Outputs (except AACTIVE) Tristate
Min
4 1 2 2 2 0
Max
Units
ns ns
18 20 20 15
ns ns ns ns
0
15
ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Figure 37 - SBI ADD BUS Timing
REFCLK
tS SIADD AJUST_REQ
tH A BIADD
tP A ACT IVE AACTIVE tP S BIADD ADATA[7:0] ADP, APL, AV5 tZ S BIADD ADATA[7:0] ADP, APL, AV5
Figure 38 - SBI ADD BUS Collision Avoidance Timing
ADETECT[n]
tP OUTEN ADATA[7:0] ADP, APL, AV5
tZ OUTEN
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Table 48 - Clock/Data Input (Figure 39) Symbol Description
RCLK[2:0] Frequency RCLK[2:0] Duty Cycle tSRD tHRD RD[2:0] Set-Up Time RD[2:0] Hold Time 40 1 2
Min
Max
51.84 60
Units
MHz % ns ns
Figure 39 - Receive Data Timing
RCLK[n] tS RD RD[n] tH RD
Table 49 - Clock/Data Output (Figure 40) Symbol Description
TCLK[2:0] Frequency TCLK[2:0] Duty Cycle tPTD TCLK[2:0] Low to TD[2:0] Valid 40 3
Min
Max
51.84 60 12
Units
MHz % ns
Figure 40 - Transmit Data Timing
TCLK[n] tP TD TD[n]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Table 50 - PCI Interface (Figure 41) Symbol Description
PCICLK Frequency (See Note 1) PCICLK Duty Cycle tSPCI tHPCI tPPCI tZPCI tZNPCI All PCI Input and Bi-directional Setup time to PCICLK All PCI Input and Bi-directional Hold time to PCICLK PCICLK to all PCI Outputs Valid PCI Output active from PCICLK to Tristate All PCI Outputs Tristate from PCICLK to active 2
Min
25 40 4 0.5 2
Max
66 60
Units
MHz % ns ns
8.5 14
ns ns ns
Notes on PCI Timing:
1. PCICLK cannot change frequency without resetting the FREEDM-84P672 device. 2. The phrase "all PCI Outputs" in the above table excludes PCIINTB and PCICLKO.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Figure 41 - PCI Interface Timing
PCICLK tS PCI INPUT tP PCI OUTPUT tZ PCI TRISTATE OUTPUT tZN PCI TRISTATE OUTPUT tH
PCI
PCI
PCI
PCI
Data Valid
PCI
Data Valid
Table 51 - JTAG Port Interface (Figure 42) Symbol Description
TCK Frequency TCK Duty Cycle tSTMS tHTMS tSTDI tHTDI tPTDO TMS Set-up time to TCK TMS Hold time to TCK TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid 40 50 50 50 50 2 60
Min
Max
1 60
Units
MHz % ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
Figure 42 - JTAG Port Interface Timing
TCK tS TMS TMS tS TDI TDI tH TDI tH TMS
TCK tP TDO TDO
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
18
ORDERING AND THERMAL INFORMATION Table 52 - FREEDM-84P672 Ordering Information PART NO.
PM7384-BI
DESCRIPTION
352 Enhanced Ball Grid Array (SBGA)
Table 53 - FREEDM-84P672 Thermal Information PART NO.
PM7384-BI
CASE TEMPERATURE
-40C to +85C
Theta Ja
19 C/W
Theta Jc
<1 C/W
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
19
MECHANICAL INFORMATION Figure 43 - 352 Pin Enhanced Ball Grid Array (SBGA)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672
CONTACTING PMC-SIERRA, INC.
PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. FREEDM is a trademark of PMC-Sierra, Inc. The technology discussed is protected by one or more of the following Patents: U.S. Patent Nos. 5,640,398 and 6,188,699 Can. Patent No. 2,161,921 Relevant patent applications and other patents may also exist. (c) 2001 PMC-Sierra, Inc PMC-1990445 (r5) ref PMC-1981262 (r4) Issue date: August 2001
PMC-Sierra, Inc.
8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

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